[PATCH 0/5] drm-intel-collector - update

[PATCH 0/5] drm-intel-collector - update

[Rodrigo Vivi]

This is another drm-intel-collector updated notice:
http://cgit.freedesktop.org/~vivijim/drm-intel/log/?h=drm-intel-collector

Here goes the update list in order for better reviewers assignment:

Patch     drm/i915: Asynchronously perform the set-base for a simple modeset - Reviewed
Patch     drm/i915: parse backlight modulation frequency from the BIOS VBT - Reviewed
Patch     drm/i915: i830M has watermarks like i855 - Reviewer:
Patch     drm/i915: vlv: W/a for hotplug/manual VGA detection - Reviewer:
Patch     drm/i915: Only use read-back pipe config - Reviewer:

Please let me know if I'm missing any patch that should be here.
And I'll skip/delay next update because I'll come back from vacations only Jan 6th.

Cheers,
Rodrigo.


Chris Wilson (1):
  drm/i915: Asynchronously perform the set-base for a simple modeset

Daniel Vetter (2):
  drm/i915: i830M has watermarks like i855
  drm/i915: Only use read-back pipe config

Imre Deak (1):
  drm/i915: vlv: W/a for hotplug/manual VGA detection

Jani Nikula (1):
  drm/i915: parse backlight modulation frequency from the BIOS VBT

 drivers/gpu/drm/i915/i915_drv.h      |  5 ++++
 drivers/gpu/drm/i915/i915_reg.h      |  3 ++
 drivers/gpu/drm/i915/intel_bios.c    | 29 ++++++++++++++++++
 drivers/gpu/drm/i915/intel_bios.h    | 16 ++++++++++
 drivers/gpu/drm/i915/intel_display.c | 14 ++++++---
 drivers/gpu/drm/i915/intel_pm.c      | 58 +++++++++++++++---------------------
 6 files changed, 87 insertions(+), 38 deletions(-)

-- 
1.8.3.1

[PATCH 1/5] drm/i915: Asynchronously perform the set-base for a simple modeset

[Rodrigo Vivi]

From: Chris Wilson <chris@chris-wilson.co.uk>

A simple modeset, where we only wish to switch over to a new framebuffer
such as the transition from fbcon to X, takes around 30-60ms. This is
due to three factors:

1. We need to make sure the fb->obj is in the display domain, which
incurs a cache flush to ensure no dirt is left on the scanout.

2. We need to flush any pending rendering before performing the mmio
so that the frame is complete before it is shown.

3. We currently wait for the vblank after the mmio to be sure that the
old fb is no longer being shown before releasing it.

(1) can only be eliminated by userspace preparing the fb->obj in advance
to already be in the display domain. This can be done through use of the
create2 ioctl, or by reusing an existing fb->obj.

However, (2) and (3) are already solved by the existing page flip
mechanism, and it is surprisingly trivial to wire them up for use in the
set-base fast path. Though it can be argued that this represents a
subtle ABI break in that the set_config ioctl now returns before the old
framebuffer is unpinned. The danger is that userspace will start to
modify it before it is no longer being shown, however we should be able
to prevent that through proper domain tracking.

By combining all of the above, we can achieve an instaneous set_config:

[     6.601] (II) intel(0): switch to mode 2560x1440@60.0 on pipe 0 using DP2, position (0, 0), rotation normal
[     6.601] (II) intel(0): Setting screen physical size to 677 x 381

v2 (by Vivi): page_flip_flag was added to intel_crtc_page_flip
              in a previous commit. using 0.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
---
 drivers/gpu/drm/i915/intel_display.c | 11 +++++++----
 1 file changed, 7 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 976a9ed..ca6cd5d 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -9990,10 +9990,13 @@ static int intel_crtc_set_config(struct drm_mode_set *set)
 		ret = intel_set_mode(set->crtc, set->mode,
 				     set->x, set->y, set->fb);
 	} else if (config->fb_changed) {
-		intel_crtc_wait_for_pending_flips(set->crtc);
-
-		ret = intel_pipe_set_base(set->crtc,
-					  set->x, set->y, set->fb);
+		if (to_intel_framebuffer(set->fb)->obj->ring == NULL ||
+		    save_set.x != set->x || save_set.y != set->y ||
+		    intel_crtc_page_flip(set->crtc, set->fb, NULL, 0)) {
+			intel_crtc_wait_for_pending_flips(set->crtc);
+			ret = intel_pipe_set_base(set->crtc,
+						  set->x, set->y, set->fb);
+		}
 	}
 
 	if (ret) {
-- 
1.8.3.1

[PATCH 2/5] drm/i915: parse backlight modulation frequency from the BIOS VBT

[Rodrigo Vivi]

From: Jani Nikula <jani.nikula@intel.com>

We don't actually do anything with the information yet, but parse and
log what's in the VBT.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
---
 drivers/gpu/drm/i915/i915_drv.h   |  5 +++++
 drivers/gpu/drm/i915/intel_bios.c | 29 +++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_bios.h | 16 ++++++++++++++++
 3 files changed, 50 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index fca2eb6..5f0e4a7 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1184,6 +1184,11 @@ struct intel_vbt_data {
 	int edp_bpp;
 	struct edp_power_seq edp_pps;
 
+	struct {
+		u16 pwm_freq_hz;
+		bool active_low_pwm;
+	} backlight;
+
 	/* MIPI DSI */
 	struct {
 		u16 panel_id;
diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
index f88e507..f220419 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -281,6 +281,34 @@ parse_lfp_panel_data(struct drm_i915_private *dev_priv,
 	}
 }
 
+static void
+parse_lfp_backlight(struct drm_i915_private *dev_priv, struct bdb_header *bdb)
+{
+	const struct bdb_lfp_backlight_data *backlight_data;
+	const struct bdb_lfp_backlight_data_entry *entry;
+
+	backlight_data = find_section(bdb, BDB_LVDS_BACKLIGHT);
+	if (!backlight_data)
+		return;
+
+	if (backlight_data->entry_size != sizeof(backlight_data->data[0])) {
+		DRM_DEBUG_KMS("Unsupported backlight data entry size %u\n",
+			      backlight_data->entry_size);
+		return;
+	}
+
+	entry = &backlight_data->data[panel_type];
+
+	dev_priv->vbt.backlight.pwm_freq_hz = entry->pwm_freq_hz;
+	dev_priv->vbt.backlight.active_low_pwm = entry->active_low_pwm;
+	DRM_DEBUG_KMS("VBT backlight PWM modulation frequency %u Hz, "
+		      "active %s, min brightness %u, level %u\n",
+		      dev_priv->vbt.backlight.pwm_freq_hz,
+		      dev_priv->vbt.backlight.active_low_pwm ? "low" : "high",
+		      entry->min_brightness,
+		      backlight_data->level[panel_type]);
+}
+
 /* Try to find sdvo panel data */
 static void
 parse_sdvo_panel_data(struct drm_i915_private *dev_priv,
@@ -894,6 +922,7 @@ intel_parse_bios(struct drm_device *dev)
 	parse_general_features(dev_priv, bdb);
 	parse_general_definitions(dev_priv, bdb);
 	parse_lfp_panel_data(dev_priv, bdb);
+	parse_lfp_backlight(dev_priv, bdb);
 	parse_sdvo_panel_data(dev_priv, bdb);
 	parse_sdvo_device_mapping(dev_priv, bdb);
 	parse_device_mapping(dev_priv, bdb);
diff --git a/drivers/gpu/drm/i915/intel_bios.h b/drivers/gpu/drm/i915/intel_bios.h
index 81ed58c..282de5e 100644
--- a/drivers/gpu/drm/i915/intel_bios.h
+++ b/drivers/gpu/drm/i915/intel_bios.h
@@ -373,6 +373,22 @@ struct bdb_lvds_lfp_data {
 	struct bdb_lvds_lfp_data_entry data[16];
 } __packed;
 
+struct bdb_lfp_backlight_data_entry {
+	u8 type:2;
+	u8 active_low_pwm:1;
+	u8 obsolete1:5;
+	u16 pwm_freq_hz;
+	u8 min_brightness;
+	u8 obsolete2;
+	u8 obsolete3;
+} __packed;
+
+struct bdb_lfp_backlight_data {
+	u8 entry_size;
+	struct bdb_lfp_backlight_data_entry data[16];
+	u8 level[16];
+} __packed;
+
 struct aimdb_header {
 	char signature[16];
 	char oem_device[20];
-- 
1.8.3.1

[PATCH 3/5] drm/i915: i830M has watermarks like i855

[Rodrigo Vivi]

From: Daniel Vetter <daniel.vetter@ffwll.ch>

So shuffle the checks around a bit. Also give all the structs and
functions proper prefixes: i830_ for the dual-pipe mobile platforms
and i845_ for the two single-pipe desktop platforms.

Note that the max fifo value isn't actually correct for the i830M, but
since we don't frob the fifo split we don't actually need it. This is
different for some gen3 devices where we need the full fifo for self
refresh mode.

Cc: Thomas Richter <richter@rus.uni-stuttgart.de>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 53 +++++++++++++++--------------------------
 1 file changed, 19 insertions(+), 34 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index bcb8470..465304a 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -824,7 +824,7 @@ static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
 	return size;
 }
 
-static int i85x_get_fifo_size(struct drm_device *dev, int plane)
+static int i830_get_fifo_size(struct drm_device *dev, int plane)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	uint32_t dsparb = I915_READ(DSPARB);
@@ -857,21 +857,6 @@ static int i845_get_fifo_size(struct drm_device *dev, int plane)
 	return size;
 }
 
-static int i830_get_fifo_size(struct drm_device *dev, int plane)
-{
-	struct drm_i915_private *dev_priv = dev->dev_private;
-	uint32_t dsparb = I915_READ(DSPARB);
-	int size;
-
-	size = dsparb & 0x7f;
-	size >>= 1; /* Convert to cachelines */
-
-	DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
-		      plane ? "B" : "A", size);
-
-	return size;
-}
-
 /* Pineview has different values for various configs */
 static const struct intel_watermark_params pineview_display_wm = {
 	PINEVIEW_DISPLAY_FIFO,
@@ -950,14 +935,14 @@ static const struct intel_watermark_params i915_wm_info = {
 	2,
 	I915_FIFO_LINE_SIZE
 };
-static const struct intel_watermark_params i855_wm_info = {
+static const struct intel_watermark_params i830_wm_info = {
 	I855GM_FIFO_SIZE,
 	I915_MAX_WM,
 	1,
 	2,
 	I830_FIFO_LINE_SIZE
 };
-static const struct intel_watermark_params i830_wm_info = {
+static const struct intel_watermark_params i845_wm_info = {
 	I830_FIFO_SIZE,
 	I915_MAX_WM,
 	1,
@@ -1574,7 +1559,7 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc)
 	else if (!IS_GEN2(dev))
 		wm_info = &i915_wm_info;
 	else
-		wm_info = &i855_wm_info;
+		wm_info = &i830_wm_info;
 
 	fifo_size = dev_priv->display.get_fifo_size(dev, 0);
 	crtc = intel_get_crtc_for_plane(dev, 0);
@@ -1681,7 +1666,7 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc)
 	}
 }
 
-static void i830_update_wm(struct drm_crtc *unused_crtc)
+static void i845_update_wm(struct drm_crtc *unused_crtc)
 {
 	struct drm_device *dev = unused_crtc->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -1696,7 +1681,7 @@ static void i830_update_wm(struct drm_crtc *unused_crtc)
 
 	adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
 	planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
-				       &i830_wm_info,
+				       &i845_wm_info,
 				       dev_priv->display.get_fifo_size(dev, 0),
 				       4, latency_ns);
 	fwater_lo = I915_READ(FW_BLC) & ~0xfff;
@@ -6180,21 +6165,21 @@ void intel_init_pm(struct drm_device *dev)
 		dev_priv->display.update_wm = i9xx_update_wm;
 		dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
 		dev_priv->display.init_clock_gating = gen3_init_clock_gating;
-	} else if (IS_I865G(dev)) {
-		dev_priv->display.update_wm = i830_update_wm;
-		dev_priv->display.init_clock_gating = i85x_init_clock_gating;
-		dev_priv->display.get_fifo_size = i830_get_fifo_size;
-	} else if (IS_I85X(dev)) {
-		dev_priv->display.update_wm = i9xx_update_wm;
-		dev_priv->display.get_fifo_size = i85x_get_fifo_size;
-		dev_priv->display.init_clock_gating = i85x_init_clock_gating;
-	} else {
-		dev_priv->display.update_wm = i830_update_wm;
-		dev_priv->display.init_clock_gating = i830_init_clock_gating;
-		if (IS_845G(dev))
+	} else if (IS_GEN2(dev)) {
+		if (INTEL_INFO(dev)->num_pipes == 1) {
+			dev_priv->display.update_wm = i845_update_wm;
 			dev_priv->display.get_fifo_size = i845_get_fifo_size;
-		else
+		} else {
+			dev_priv->display.update_wm = i9xx_update_wm;
 			dev_priv->display.get_fifo_size = i830_get_fifo_size;
+		}
+
+		if (IS_I85X(dev) || IS_I865G(dev))
+			dev_priv->display.init_clock_gating = i85x_init_clock_gating;
+		else
+			dev_priv->display.init_clock_gating = i830_init_clock_gating;
+	} else {
+		DRM_ERROR("unexpected fall-through in intel_init_pm\n");
 	}
 }
 
-- 
1.8.3.1

[PATCH 4/5] drm/i915: vlv: W/a for hotplug/manual VGA detection

[Rodrigo Vivi]

From: Imre Deak <imre.deak@intel.com>

At least on my VLV stepping VGA detection doesn't work in certain cases.
One such case is when all pipes are off and VGA is plugged in. Another
case reported by Joonas Lahtinen (also on the same stepping) is booting
with VGA disconnected where we incorrectly report that VGA is connected.
At least in the first case writing the FORCE bit in the ADPA reg will
get stuck, i.e. the detection never completes.

Both cases seem to be solved by disabling DPIO clock gating based on the
PSR state. As I haven't found any trace that this would be a known
issue, I can only speculate that both the DPIO HW block and the HW
block responsible for VGA detection uses the same clock source which gets
gated even though PSR is inactive.

I haven't measured if and how this change affects our power savings.

Reported-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 3 +++
 drivers/gpu/drm/i915/intel_pm.c | 5 +++++
 2 files changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f1eece4..726c3ce 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1451,6 +1451,9 @@
 # define I965_FT_CLOCK_GATE_DISABLE		(1 << 1)
 # define I965_DM_CLOCK_GATE_DISABLE		(1 << 0)
 
+#define DPPSR_CGDIS_VLV                (dev_priv->info->display_mmio_offset + 0x6204)
+# define DPIOUNIT_PSR_CLOCK_GATING_DISABLE     (1 << 6)
+
 #define RENCLK_GATE_D2		0x6208
 #define VF_UNIT_CLOCK_GATE_DISABLE		(1 << 9)
 #define GS_UNIT_CLOCK_GATE_DISABLE		(1 << 7)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 465304a..4208065 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5438,6 +5438,11 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
 
 	I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
 
+	/* Wa to make VGA hotplug and manual detection work. */
+	val = I915_READ(DPPSR_CGDIS_VLV);
+	val |= DPIOUNIT_PSR_CLOCK_GATING_DISABLE;
+	I915_WRITE(DPIOUNIT_PSR_CLOCK_GATING_DISABLE, val);
+
 	/* WaDisableEarlyCull:vlv */
 	I915_WRITE(_3D_CHICKEN3,
 		   _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
-- 
1.8.3.1

[PATCH 5/5] drm/i915: Only use read-back pipe config

[Rodrigo Vivi]

From: Daniel Vetter <daniel.vetter@ffwll.ch>

This way we'll catch bugs in our code where we depend upon pipe config
state not (yet) read out much quicker, through a simple dpms on/off
cycle.

This will blow up all over the place for now, hence just a quick idea
to toss out there.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
---
 drivers/gpu/drm/i915/intel_display.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index ca6cd5d..04efe1b 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -9492,6 +9492,9 @@ check_crtc_state(struct drm_device *dev)
 			intel_dump_pipe_config(crtc, &crtc->config,
 					       "[sw state]");
 		}
+
+		/* Make sure our code only depends upon stuff we read back. */
+		memcpy(&pipe_config, &crtc->config, sizeof(pipe_config));
 	}
 }
 
-- 
1.8.3.1

Re: [PATCH 2/5] drm/i915: parse backlight modulation frequency from the BIOS VBT

[Daniel Vetter]

On Sat, Dec 14, 2013 at 08:38:29PM -0200, Rodrigo Vivi wrote:
> From: Jani Nikula <jani.nikula@intel.com>
> 
> We don't actually do anything with the information yet, but parse and
> log what's in the VBT.
> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>

Queued for -next, thanks for the patch.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH 4/5] drm/i915: vlv: W/a for hotplug/manual VGA detection

[Imre Deak]

On Sat, 2013-12-14 at 20:38 -0200, Rodrigo Vivi wrote:
> From: Imre Deak <imre.deak@intel.com>
> 
> At least on my VLV stepping VGA detection doesn't work in certain cases.
> One such case is when all pipes are off and VGA is plugged in. Another
> case reported by Joonas Lahtinen (also on the same stepping) is booting
> with VGA disconnected where we incorrectly report that VGA is connected.
> At least in the first case writing the FORCE bit in the ADPA reg will
> get stuck, i.e. the detection never completes.
> 
> Both cases seem to be solved by disabling DPIO clock gating based on the
> PSR state. As I haven't found any trace that this would be a known
> issue, I can only speculate that both the DPIO HW block and the HW
> block responsible for VGA detection uses the same clock source which gets
> gated even though PSR is inactive.
> 
> I haven't measured if and how this change affects our power savings.
> 
> Reported-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>

Please ignore this, I'll send a v2.

> ---
>  drivers/gpu/drm/i915/i915_reg.h | 3 +++
>  drivers/gpu/drm/i915/intel_pm.c | 5 +++++
>  2 files changed, 8 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index f1eece4..726c3ce 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1451,6 +1451,9 @@
>  # define I965_FT_CLOCK_GATE_DISABLE		(1 << 1)
>  # define I965_DM_CLOCK_GATE_DISABLE		(1 << 0)
>  
> +#define DPPSR_CGDIS_VLV                (dev_priv->info->display_mmio_offset + 0x6204)
> +# define DPIOUNIT_PSR_CLOCK_GATING_DISABLE     (1 << 6)
> +
>  #define RENCLK_GATE_D2		0x6208
>  #define VF_UNIT_CLOCK_GATE_DISABLE		(1 << 9)
>  #define GS_UNIT_CLOCK_GATE_DISABLE		(1 << 7)
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 465304a..4208065 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -5438,6 +5438,11 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
>  
>  	I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
>  
> +	/* Wa to make VGA hotplug and manual detection work. */
> +	val = I915_READ(DPPSR_CGDIS_VLV);
> +	val |= DPIOUNIT_PSR_CLOCK_GATING_DISABLE;
> +	I915_WRITE(DPIOUNIT_PSR_CLOCK_GATING_DISABLE, val);
> +
>  	/* WaDisableEarlyCull:vlv */
>  	I915_WRITE(_3D_CHICKEN3,
>  		   _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));

Re: [PATCH 3/5] drm/i915: i830M has watermarks like i855

[Ville Syrjälä]

On Sat, Dec 14, 2013 at 08:38:30PM -0200, Rodrigo Vivi wrote:
> From: Daniel Vetter <daniel.vetter@ffwll.ch>
> 
> So shuffle the checks around a bit. Also give all the structs and
> functions proper prefixes: i830_ for the dual-pipe mobile platforms
> and i845_ for the two single-pipe desktop platforms.
> 
> Note that the max fifo value isn't actually correct for the i830M, but
> since we don't frob the fifo split we don't actually need it. This is
> different for some gen3 devices where we need the full fifo for self
> refresh mode.
> 
> Cc: Thomas Richter <richter@rus.uni-stuttgart.de>
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/intel_pm.c | 53 +++++++++++++++--------------------------
>  1 file changed, 19 insertions(+), 34 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index bcb8470..465304a 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -824,7 +824,7 @@ static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
>  	return size;
>  }
>  
> -static int i85x_get_fifo_size(struct drm_device *dev, int plane)
> +static int i830_get_fifo_size(struct drm_device *dev, int plane)
>  {
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  	uint32_t dsparb = I915_READ(DSPARB);
> @@ -857,21 +857,6 @@ static int i845_get_fifo_size(struct drm_device *dev, int plane)
>  	return size;
>  }
>  
> -static int i830_get_fifo_size(struct drm_device *dev, int plane)
> -{
> -	struct drm_i915_private *dev_priv = dev->dev_private;
> -	uint32_t dsparb = I915_READ(DSPARB);
> -	int size;
> -
> -	size = dsparb & 0x7f;
> -	size >>= 1; /* Convert to cachelines */
> -
> -	DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
> -		      plane ? "B" : "A", size);
> -
> -	return size;
> -}
> -
>  /* Pineview has different values for various configs */
>  static const struct intel_watermark_params pineview_display_wm = {
>  	PINEVIEW_DISPLAY_FIFO,
> @@ -950,14 +935,14 @@ static const struct intel_watermark_params i915_wm_info = {
>  	2,
>  	I915_FIFO_LINE_SIZE
>  };
> -static const struct intel_watermark_params i855_wm_info = {
> +static const struct intel_watermark_params i830_wm_info = {
>  	I855GM_FIFO_SIZE,
>  	I915_MAX_WM,
>  	1,
>  	2,
>  	I830_FIFO_LINE_SIZE
>  };
> -static const struct intel_watermark_params i830_wm_info = {
> +static const struct intel_watermark_params i845_wm_info = {
>  	I830_FIFO_SIZE,
>  	I915_MAX_WM,
>  	1,
> @@ -1574,7 +1559,7 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc)
>  	else if (!IS_GEN2(dev))
>  		wm_info = &i915_wm_info;
>  	else
> -		wm_info = &i855_wm_info;
> +		wm_info = &i830_wm_info;
>  
>  	fifo_size = dev_priv->display.get_fifo_size(dev, 0);
>  	crtc = intel_get_crtc_for_plane(dev, 0);
> @@ -1681,7 +1666,7 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc)
>  	}
>  }
>  
> -static void i830_update_wm(struct drm_crtc *unused_crtc)
> +static void i845_update_wm(struct drm_crtc *unused_crtc)
>  {
>  	struct drm_device *dev = unused_crtc->dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> @@ -1696,7 +1681,7 @@ static void i830_update_wm(struct drm_crtc *unused_crtc)
>  
>  	adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
>  	planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
> -				       &i830_wm_info,
> +				       &i845_wm_info,
>  				       dev_priv->display.get_fifo_size(dev, 0),
>  				       4, latency_ns);
>  	fwater_lo = I915_READ(FW_BLC) & ~0xfff;
> @@ -6180,21 +6165,21 @@ void intel_init_pm(struct drm_device *dev)
>  		dev_priv->display.update_wm = i9xx_update_wm;
>  		dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
>  		dev_priv->display.init_clock_gating = gen3_init_clock_gating;
> -	} else if (IS_I865G(dev)) {
> -		dev_priv->display.update_wm = i830_update_wm;
> -		dev_priv->display.init_clock_gating = i85x_init_clock_gating;
> -		dev_priv->display.get_fifo_size = i830_get_fifo_size;
> -	} else if (IS_I85X(dev)) {
> -		dev_priv->display.update_wm = i9xx_update_wm;
> -		dev_priv->display.get_fifo_size = i85x_get_fifo_size;
> -		dev_priv->display.init_clock_gating = i85x_init_clock_gating;
> -	} else {
> -		dev_priv->display.update_wm = i830_update_wm;
> -		dev_priv->display.init_clock_gating = i830_init_clock_gating;
> -		if (IS_845G(dev))
> +	} else if (IS_GEN2(dev)) {
> +		if (INTEL_INFO(dev)->num_pipes == 1) {
> +			dev_priv->display.update_wm = i845_update_wm;
>  			dev_priv->display.get_fifo_size = i845_get_fifo_size;
> -		else
> +		} else {
> +			dev_priv->display.update_wm = i9xx_update_wm;
>  			dev_priv->display.get_fifo_size = i830_get_fifo_size;
> +		}
> +
> +		if (IS_I85X(dev) || IS_I865G(dev))
> +			dev_priv->display.init_clock_gating = i85x_init_clock_gating;
> +		else
> +			dev_priv->display.init_clock_gating = i830_init_clock_gating;
> +	} else {
> +		DRM_ERROR("unexpected fall-through in intel_init_pm\n");
>  	}
>  }
>  
> -- 
> 1.8.3.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC