From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH v3 2/2] drm/i915: vlv: W/a for hotplug/manual VGA detection Date: Fri, 10 Jan 2014 15:04:46 +0200 Message-ID: <20140110130445.GA9454@intel.com> References: <1389280096-1032-1-git-send-email-imre.deak@intel.com> <1389280096-1032-2-git-send-email-imre.deak@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTP id 4553C106097 for ; Fri, 10 Jan 2014 05:04:49 -0800 (PST) Content-Disposition: inline In-Reply-To: <1389280096-1032-2-git-send-email-imre.deak@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org To: Imre Deak Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Thu, Jan 09, 2014 at 05:08:16PM +0200, Imre Deak wrote: > VGA detection requires the reference clock to be on, so make sure this > is the case. > = > This fixes VGA hotplug/manual detection where all pipes are off and so > we would normally disable all clocks. > = > v2: > - Instead of disabling PSR clock gating, force the reference clock on > through the DPLL_A register. (Kin Chan S ) > = > v3: > - Move enabling of the clock to intel_reset_dpio() and use the DPLL_B > register instead, where we already have a similar tweak for the CRI > clock. (Ville) > = > Reported-by: Joonas Lahtinen > Signed-off-by: Imre Deak For the series: Reviewed-by: Ville Syrj=E4l=E4 > --- > drivers/gpu/drm/i915/intel_display.c | 19 +++++++++++++++---- > 1 file changed, 15 insertions(+), 4 deletions(-) > = > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/= intel_display.c > index 3262ac4..4e2598b 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -1377,8 +1377,12 @@ static void intel_reset_dpio(struct drm_device *de= v) > if (!IS_VALLEYVIEW(dev)) > return; > = > - /* Enable the CRI clock source so we can get at the display */ > + /* > + * Enable the CRI clock source so we can get at the display and the > + * reference clock for VGA hotplug / manual detection. > + */ > I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) | > + DPLL_REFA_CLK_ENABLE_VLV | > DPLL_INTEGRATED_CRI_CLK_VLV); > = > /* > @@ -1507,9 +1511,12 @@ static void vlv_disable_pll(struct drm_i915_privat= e *dev_priv, enum pipe pipe) > /* Make sure the pipe isn't still relying on us */ > assert_pipe_disabled(dev_priv, pipe); > = > - /* Leave integrated clock source enabled */ > + /* > + * Leave integrated clock source and reference clock enabled for pipe B. > + * The latter is needed for VGA hotplug / manual detection. > + */ > if (pipe =3D=3D PIPE_B) > - val =3D DPLL_INTEGRATED_CRI_CLK_VLV; > + val =3D DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV; > I915_WRITE(DPLL(pipe), val); > POSTING_READ(DPLL(pipe)); > } > @@ -4986,7 +4993,11 @@ static void vlv_update_pll(struct intel_crtc *crtc) > = > vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000); > = > - /* Enable DPIO clock input */ > + /* > + * Enable DPIO clock input. We should never disable the reference > + * clock for pipe B, since VGA hotplug / manual detection depends > + * on it. > + */ > dpll =3D DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV | > DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV; > /* We should never disable this, set it here for state tracking */ > -- = > 1.8.4 -- = Ville Syrj=E4l=E4 Intel OTC