[PATCH v3 1/2] drm/i915: vlv: make CRI clock enabling explicit during resume

[PATCH v3 1/2] drm/i915: vlv: make CRI clock enabling explicit during resume

[Imre Deak]

intel_init_dpio() isn't called during resume, so we won't set the CRI
clock enable bit during that time. Move the enabling to
intel_reset_dpio() instead.

Note that the HW reset value for this bit is 1, so probably this patch
won't make any difference. We should still make the setting explicit,
since BIOS could change things under us.

Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index ba9d62e..3262ac4 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1367,10 +1367,6 @@ static void intel_init_dpio(struct drm_device *dev)
 	if (!IS_VALLEYVIEW(dev))
 		return;
 
-	/* Enable the CRI clock source so we can get at the display */
-	I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
-		   DPLL_INTEGRATED_CRI_CLK_VLV);
-
 	DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
 }
 
@@ -1381,6 +1377,10 @@ static void intel_reset_dpio(struct drm_device *dev)
 	if (!IS_VALLEYVIEW(dev))
 		return;
 
+	/* Enable the CRI clock source so we can get at the display */
+	I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
+		   DPLL_INTEGRATED_CRI_CLK_VLV);
+
 	/*
 	 * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
 	 *  6.	De-assert cmn_reset/side_reset. Same as VLV X0.
-- 
1.8.4

[PATCH v3 2/2] drm/i915: vlv: W/a for hotplug/manual VGA detection

[Imre Deak]

VGA detection requires the reference clock to be on, so make sure this
is the case.

This fixes VGA hotplug/manual detection where all pipes are off and so
we would normally disable all clocks.

v2:
- Instead of disabling PSR clock gating, force the reference clock on
  through the DPLL_A register. (Kin Chan S <kin.s.chan@intel.com>)

v3:
- Move enabling of the clock to intel_reset_dpio() and use the DPLL_B
  register instead, where we already have a similar tweak for the CRI
  clock. (Ville)

Reported-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 19 +++++++++++++++----
 1 file changed, 15 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 3262ac4..4e2598b 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1377,8 +1377,12 @@ static void intel_reset_dpio(struct drm_device *dev)
 	if (!IS_VALLEYVIEW(dev))
 		return;
 
-	/* Enable the CRI clock source so we can get at the display */
+	/*
+	 * Enable the CRI clock source so we can get at the display and the
+	 * reference clock for VGA hotplug / manual detection.
+	 */
 	I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
+		   DPLL_REFA_CLK_ENABLE_VLV |
 		   DPLL_INTEGRATED_CRI_CLK_VLV);
 
 	/*
@@ -1507,9 +1511,12 @@ static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
 	/* Make sure the pipe isn't still relying on us */
 	assert_pipe_disabled(dev_priv, pipe);
 
-	/* Leave integrated clock source enabled */
+	/*
+	 * Leave integrated clock source and reference clock enabled for pipe B.
+	 * The latter is needed for VGA hotplug / manual detection.
+	 */
 	if (pipe == PIPE_B)
-		val = DPLL_INTEGRATED_CRI_CLK_VLV;
+		val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
 	I915_WRITE(DPLL(pipe), val);
 	POSTING_READ(DPLL(pipe));
 }
@@ -4986,7 +4993,11 @@ static void vlv_update_pll(struct intel_crtc *crtc)
 
 	vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
 
-	/* Enable DPIO clock input */
+	/*
+	 * Enable DPIO clock input. We should never disable the reference
+	 * clock for pipe B, since VGA hotplug / manual detection depends
+	 * on it.
+	 */
 	dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
 		DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
 	/* We should never disable this, set it here for state tracking */
-- 
1.8.4

Re: [PATCH v3 2/2] drm/i915: vlv: W/a for hotplug/manual VGA detection

[Ville Syrjälä]

On Thu, Jan 09, 2014 at 05:08:16PM +0200, Imre Deak wrote:
> VGA detection requires the reference clock to be on, so make sure this
> is the case.
> 
> This fixes VGA hotplug/manual detection where all pipes are off and so
> we would normally disable all clocks.
> 
> v2:
> - Instead of disabling PSR clock gating, force the reference clock on
>   through the DPLL_A register. (Kin Chan S <kin.s.chan@intel.com>)
> 
> v3:
> - Move enabling of the clock to intel_reset_dpio() and use the DPLL_B
>   register instead, where we already have a similar tweak for the CRI
>   clock. (Ville)
> 
> Reported-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>

For the series:

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/intel_display.c | 19 +++++++++++++++----
>  1 file changed, 15 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 3262ac4..4e2598b 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -1377,8 +1377,12 @@ static void intel_reset_dpio(struct drm_device *dev)
>  	if (!IS_VALLEYVIEW(dev))
>  		return;
>  
> -	/* Enable the CRI clock source so we can get at the display */
> +	/*
> +	 * Enable the CRI clock source so we can get at the display and the
> +	 * reference clock for VGA hotplug / manual detection.
> +	 */
>  	I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
> +		   DPLL_REFA_CLK_ENABLE_VLV |
>  		   DPLL_INTEGRATED_CRI_CLK_VLV);
>  
>  	/*
> @@ -1507,9 +1511,12 @@ static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
>  	/* Make sure the pipe isn't still relying on us */
>  	assert_pipe_disabled(dev_priv, pipe);
>  
> -	/* Leave integrated clock source enabled */
> +	/*
> +	 * Leave integrated clock source and reference clock enabled for pipe B.
> +	 * The latter is needed for VGA hotplug / manual detection.
> +	 */
>  	if (pipe == PIPE_B)
> -		val = DPLL_INTEGRATED_CRI_CLK_VLV;
> +		val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
>  	I915_WRITE(DPLL(pipe), val);
>  	POSTING_READ(DPLL(pipe));
>  }
> @@ -4986,7 +4993,11 @@ static void vlv_update_pll(struct intel_crtc *crtc)
>  
>  	vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
>  
> -	/* Enable DPIO clock input */
> +	/*
> +	 * Enable DPIO clock input. We should never disable the reference
> +	 * clock for pipe B, since VGA hotplug / manual detection depends
> +	 * on it.
> +	 */
>  	dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
>  		DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
>  	/* We should never disable this, set it here for state tracking */
> -- 
> 1.8.4

-- 
Ville Syrjälä
Intel OTC