From mboxrd@z Thu Jan  1 00:00:00 1970
From: Jesse Barnes <jbarnes@virtuousgeek.org>
Subject: Re: [PATCH 2/3] drm/i915: don't wait for vblank after
 enabling pipe on HSW
Date: Wed, 15 Jan 2014 10:26:46 -0800
Message-ID: <20140115102646.51061351@jbarnes-desktop>
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To: Paulo Zanoni <przanoni@gmail.com>
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On Thu, 19 Dec 2013 19:12:30 -0200
Paulo Zanoni <przanoni@gmail.com> wrote:

> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
> 
> Because on Haswell, the pipe is never running at this point, so we hit
> the 50ms timeout waiting for nothing. We already have two other places
> where we wait for vblanks on haswell_crtc_enable, so we're safe.
> 
> This gets us rid of one instance of "vblank wait timed out" for each
> mode set, which means driver init and resume are also 50ms faster.
> 
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 6865fa2..f0f78d3 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3706,7 +3706,7 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
>  
>  	intel_update_watermarks(crtc);
>  	intel_enable_pipe(dev_priv, pipe,
> -			  intel_crtc->config.has_pch_encoder, false, true);
> +			  intel_crtc->config.has_pch_encoder, false, false);
>  
>  	if (intel_crtc->config.has_pch_encoder)
>  		lpt_pch_enable(crtc);

Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>

-- 
Jesse Barnes, Intel Open Source Technology Center