[PATCH 0/3] drm/i915: FIFO underrun reporting changes

[PATCH 0/3] drm/i915: FIFO underrun reporting changes

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

I've mentioned before that I had a patch to re-enable FIFO underrun
reporting after a certain time. Well, here it is.

Based on the recent quick discussion I also took the opportunity to
convert GMCH platforms to use the same underrung reporting logic as
we use for PCH platforms.

And then, there's a patch to make underrun reports DRM_ERRORs. Not
sure how many bug reports we'd be getting, but we should do that
eventually anyway. We do have some cases (eg. too much sprite
scaling vs. cdclk frequency) that can cause underruns currently,
and the watermark code still has some issues, but under typical
use w/o sprites, I wouldn't expect underruns.

Ville Syrjälä (3):
  drm/i915: Limit FIFO underrun reports on GMCH platforms
  drm/i915: Make underruns DRM_ERROR
  drm/i915: Re-enable underrun reporting after 2 secs

 drivers/gpu/drm/i915/i915_drv.h      |  1 +
 drivers/gpu/drm/i915/i915_irq.c      | 98 ++++++++++++++++++++++++++----------
 drivers/gpu/drm/i915/intel_display.c |  3 ++
 3 files changed, 75 insertions(+), 27 deletions(-)

-- 
1.8.3.2

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[PATCH 1/3] drm/i915: Limit FIFO underrun reports on GMCH platforms

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Currently we print all pipe underruns on GMCH platforms. Hook up the
same logic we use on PCH platforms where we disable the underrun
reporting after the first underrun.

Underruns don't actually generate interrupts themselves on GMCH
platforms, we just can detect them whenever we service other
interrupts. So we don't have any enable bits to worry about. We just
need to remember to clear the underrun status when enabling underrun
reporting.

Note that the underrun handling needs to be moved to the non-locked
pipe_stats[] loop in the interrupt handlers to avoid having to rework
the locking in intel_set_cpu_fifo_underrun_reporting().

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c      | 51 +++++++++++++++++++++++-------------
 drivers/gpu/drm/i915/intel_display.c |  3 +++
 2 files changed, 36 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index b9b3bde..e5cba0b 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -232,6 +232,18 @@ static bool cpt_can_enable_serr_int(struct drm_device *dev)
 	return true;
 }
 
+static void i9xx_clear_fifo_underrun(struct drm_device *dev, enum pipe pipe)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	u32 reg = PIPESTAT(pipe);
+	u32 pipestat = I915_READ(reg) & 0x7fff0000;
+
+	assert_spin_locked(&dev_priv->irq_lock);
+
+	I915_WRITE(reg, pipestat | PIPE_FIFO_UNDERRUN_STATUS);
+	POSTING_READ(reg);
+}
+
 static void ironlake_set_fifo_underrun_reporting(struct drm_device *dev,
 						 enum pipe pipe, bool enable)
 {
@@ -393,7 +405,9 @@ bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
 
 	intel_crtc->cpu_fifo_underrun_disabled = !enable;
 
-	if (IS_GEN5(dev) || IS_GEN6(dev))
+	if (enable && (INTEL_INFO(dev)->gen < 5 || IS_VALLEYVIEW(dev)))
+		i9xx_clear_fifo_underrun(dev, pipe);
+	else if (IS_GEN5(dev) || IS_GEN6(dev))
 		ironlake_set_fifo_underrun_reporting(dev, pipe, enable);
 	else if (IS_GEN7(dev))
 		ivybridge_set_fifo_underrun_reporting(dev, pipe, enable);
@@ -1439,12 +1453,8 @@ static irqreturn_t valleyview_irq_handler(int irq, void *arg)
 			/*
 			 * Clear the PIPE*STAT regs before the IIR
 			 */
-			if (pipe_stats[pipe] & 0x8000ffff) {
-				if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
-					DRM_DEBUG_DRIVER("pipe %c underrun\n",
-							 pipe_name(pipe));
+			if (pipe_stats[pipe] & 0x8000ffff)
 				I915_WRITE(reg, pipe_stats[pipe]);
-			}
 		}
 		spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 
@@ -1459,6 +1469,10 @@ static irqreturn_t valleyview_irq_handler(int irq, void *arg)
 
 			if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
 				i9xx_pipe_crc_irq_handler(dev, pipe);
+
+			if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
+			    intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
+				DRM_DEBUG_DRIVER("pipe %c underrun\n", pipe_name(pipe));
 		}
 
 		/* Consume port.  Then clear IIR or we'll miss events */
@@ -3188,12 +3202,8 @@ static irqreturn_t i8xx_irq_handler(int irq, void *arg)
 			/*
 			 * Clear the PIPE*STAT regs before the IIR
 			 */
-			if (pipe_stats[pipe] & 0x8000ffff) {
-				if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
-					DRM_DEBUG_DRIVER("pipe %c underrun\n",
-							 pipe_name(pipe));
+			if (pipe_stats[pipe] & 0x8000ffff)
 				I915_WRITE(reg, pipe_stats[pipe]);
-			}
 		}
 		spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 
@@ -3216,6 +3226,10 @@ static irqreturn_t i8xx_irq_handler(int irq, void *arg)
 
 			if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
 				i9xx_pipe_crc_irq_handler(dev, pipe);
+
+			if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
+			    intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
+				DRM_DEBUG_DRIVER("pipe %c underrun\n", pipe_name(pipe));
 		}
 
 		iir = new_iir;
@@ -3369,9 +3383,6 @@ static irqreturn_t i915_irq_handler(int irq, void *arg)
 
 			/* Clear the PIPE*STAT regs before the IIR */
 			if (pipe_stats[pipe] & 0x8000ffff) {
-				if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
-					DRM_DEBUG_DRIVER("pipe %c underrun\n",
-							 pipe_name(pipe));
 				I915_WRITE(reg, pipe_stats[pipe]);
 				irq_received = true;
 			}
@@ -3416,6 +3427,10 @@ static irqreturn_t i915_irq_handler(int irq, void *arg)
 
 			if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
 				i9xx_pipe_crc_irq_handler(dev, pipe);
+
+			if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
+			    intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
+				DRM_DEBUG_DRIVER("pipe %c underrun\n", pipe_name(pipe));
 		}
 
 		if (blc_event || (iir & I915_ASLE_INTERRUPT))
@@ -3610,9 +3625,6 @@ static irqreturn_t i965_irq_handler(int irq, void *arg)
 			 * Clear the PIPE*STAT regs before the IIR
 			 */
 			if (pipe_stats[pipe] & 0x8000ffff) {
-				if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
-					DRM_DEBUG_DRIVER("pipe %c underrun\n",
-							 pipe_name(pipe));
 				I915_WRITE(reg, pipe_stats[pipe]);
 				irq_received = true;
 			}
@@ -3663,8 +3675,11 @@ static irqreturn_t i965_irq_handler(int irq, void *arg)
 
 			if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
 				i9xx_pipe_crc_irq_handler(dev, pipe);
-		}
 
+			if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
+			    intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
+				DRM_DEBUG_DRIVER("pipe %c underrun\n", pipe_name(pipe));
+		}
 
 		if (blc_event || (iir & I915_ASLE_INTERRUPT))
 			intel_opregion_asle_intr(dev);
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index dde98020..6369bd7 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4146,6 +4146,7 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)
 
 	intel_update_watermarks(crtc);
 	intel_enable_pipe(dev_priv, pipe, false, is_dsi);
+	intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
 	intel_enable_primary_plane(dev_priv, plane, pipe);
 	intel_enable_planes(crtc);
 	intel_crtc_update_cursor(crtc, true);
@@ -4184,6 +4185,7 @@ static void i9xx_crtc_enable(struct drm_crtc *crtc)
 
 	intel_update_watermarks(crtc);
 	intel_enable_pipe(dev_priv, pipe, false, false);
+	intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
 	intel_enable_primary_plane(dev_priv, plane, pipe);
 	intel_enable_planes(crtc);
 	/* The fixup needs to happen before cursor is enabled */
@@ -4242,6 +4244,7 @@ static void i9xx_crtc_disable(struct drm_crtc *crtc)
 	intel_disable_planes(crtc);
 	intel_disable_primary_plane(dev_priv, plane, pipe);
 
+	intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
 	intel_disable_pipe(dev_priv, pipe);
 
 	i9xx_pfit_disable(intel_crtc);
-- 
1.8.3.2

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Re: [PATCH 1/3] drm/i915: Limit FIFO underrun reports on GMCH platforms

[Paulo Zanoni]

2014/1/17  <ville.syrjala@linux.intel.com>:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Currently we print all pipe underruns on GMCH platforms. Hook up the
> same logic we use on PCH platforms where we disable the underrun
> reporting after the first underrun.
>
> Underruns don't actually generate interrupts themselves on GMCH
> platforms, we just can detect them whenever we service other
> interrupts. So we don't have any enable bits to worry about. We just
> need to remember to clear the underrun status when enabling underrun
> reporting.
>
> Note that the underrun handling needs to be moved to the non-locked
> pipe_stats[] loop in the interrupt handlers to avoid having to rework
> the locking in intel_set_cpu_fifo_underrun_reporting().
>

It all looks sane and according to the Gen 4 spec I have, but I can't
check stuff like "where's the best place to call the funcs at crtc
enable/disable?", so I'll just trust you here.

You would have got extra points if you defined a nice macro instead of
continuing to use the hardcoded 0x8000ffff and 0x7fff0000 values :)

Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>


> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_irq.c      | 51 +++++++++++++++++++++++-------------
>  drivers/gpu/drm/i915/intel_display.c |  3 +++
>  2 files changed, 36 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index b9b3bde..e5cba0b 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -232,6 +232,18 @@ static bool cpt_can_enable_serr_int(struct drm_device *dev)
>         return true;
>  }
>
> +static void i9xx_clear_fifo_underrun(struct drm_device *dev, enum pipe pipe)
> +{
> +       struct drm_i915_private *dev_priv = dev->dev_private;
> +       u32 reg = PIPESTAT(pipe);
> +       u32 pipestat = I915_READ(reg) & 0x7fff0000;
> +
> +       assert_spin_locked(&dev_priv->irq_lock);
> +
> +       I915_WRITE(reg, pipestat | PIPE_FIFO_UNDERRUN_STATUS);
> +       POSTING_READ(reg);
> +}
> +
>  static void ironlake_set_fifo_underrun_reporting(struct drm_device *dev,
>                                                  enum pipe pipe, bool enable)
>  {
> @@ -393,7 +405,9 @@ bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
>
>         intel_crtc->cpu_fifo_underrun_disabled = !enable;
>
> -       if (IS_GEN5(dev) || IS_GEN6(dev))
> +       if (enable && (INTEL_INFO(dev)->gen < 5 || IS_VALLEYVIEW(dev)))
> +               i9xx_clear_fifo_underrun(dev, pipe);
> +       else if (IS_GEN5(dev) || IS_GEN6(dev))
>                 ironlake_set_fifo_underrun_reporting(dev, pipe, enable);
>         else if (IS_GEN7(dev))
>                 ivybridge_set_fifo_underrun_reporting(dev, pipe, enable);
> @@ -1439,12 +1453,8 @@ static irqreturn_t valleyview_irq_handler(int irq, void *arg)
>                         /*
>                          * Clear the PIPE*STAT regs before the IIR
>                          */
> -                       if (pipe_stats[pipe] & 0x8000ffff) {
> -                               if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
> -                                       DRM_DEBUG_DRIVER("pipe %c underrun\n",
> -                                                        pipe_name(pipe));
> +                       if (pipe_stats[pipe] & 0x8000ffff)
>                                 I915_WRITE(reg, pipe_stats[pipe]);
> -                       }
>                 }
>                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
>
> @@ -1459,6 +1469,10 @@ static irqreturn_t valleyview_irq_handler(int irq, void *arg)
>
>                         if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
>                                 i9xx_pipe_crc_irq_handler(dev, pipe);
> +
> +                       if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
> +                           intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
> +                               DRM_DEBUG_DRIVER("pipe %c underrun\n", pipe_name(pipe));
>                 }
>
>                 /* Consume port.  Then clear IIR or we'll miss events */
> @@ -3188,12 +3202,8 @@ static irqreturn_t i8xx_irq_handler(int irq, void *arg)
>                         /*
>                          * Clear the PIPE*STAT regs before the IIR
>                          */
> -                       if (pipe_stats[pipe] & 0x8000ffff) {
> -                               if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
> -                                       DRM_DEBUG_DRIVER("pipe %c underrun\n",
> -                                                        pipe_name(pipe));
> +                       if (pipe_stats[pipe] & 0x8000ffff)
>                                 I915_WRITE(reg, pipe_stats[pipe]);
> -                       }
>                 }
>                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
>
> @@ -3216,6 +3226,10 @@ static irqreturn_t i8xx_irq_handler(int irq, void *arg)
>
>                         if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
>                                 i9xx_pipe_crc_irq_handler(dev, pipe);
> +
> +                       if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
> +                           intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
> +                               DRM_DEBUG_DRIVER("pipe %c underrun\n", pipe_name(pipe));
>                 }
>
>                 iir = new_iir;
> @@ -3369,9 +3383,6 @@ static irqreturn_t i915_irq_handler(int irq, void *arg)
>
>                         /* Clear the PIPE*STAT regs before the IIR */
>                         if (pipe_stats[pipe] & 0x8000ffff) {
> -                               if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
> -                                       DRM_DEBUG_DRIVER("pipe %c underrun\n",
> -                                                        pipe_name(pipe));
>                                 I915_WRITE(reg, pipe_stats[pipe]);
>                                 irq_received = true;
>                         }
> @@ -3416,6 +3427,10 @@ static irqreturn_t i915_irq_handler(int irq, void *arg)
>
>                         if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
>                                 i9xx_pipe_crc_irq_handler(dev, pipe);
> +
> +                       if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
> +                           intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
> +                               DRM_DEBUG_DRIVER("pipe %c underrun\n", pipe_name(pipe));
>                 }
>
>                 if (blc_event || (iir & I915_ASLE_INTERRUPT))
> @@ -3610,9 +3625,6 @@ static irqreturn_t i965_irq_handler(int irq, void *arg)
>                          * Clear the PIPE*STAT regs before the IIR
>                          */
>                         if (pipe_stats[pipe] & 0x8000ffff) {
> -                               if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
> -                                       DRM_DEBUG_DRIVER("pipe %c underrun\n",
> -                                                        pipe_name(pipe));
>                                 I915_WRITE(reg, pipe_stats[pipe]);
>                                 irq_received = true;
>                         }
> @@ -3663,8 +3675,11 @@ static irqreturn_t i965_irq_handler(int irq, void *arg)
>
>                         if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
>                                 i9xx_pipe_crc_irq_handler(dev, pipe);
> -               }
>
> +                       if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
> +                           intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
> +                               DRM_DEBUG_DRIVER("pipe %c underrun\n", pipe_name(pipe));
> +               }
>
>                 if (blc_event || (iir & I915_ASLE_INTERRUPT))
>                         intel_opregion_asle_intr(dev);
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index dde98020..6369bd7 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -4146,6 +4146,7 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)
>
>         intel_update_watermarks(crtc);
>         intel_enable_pipe(dev_priv, pipe, false, is_dsi);
> +       intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
>         intel_enable_primary_plane(dev_priv, plane, pipe);
>         intel_enable_planes(crtc);
>         intel_crtc_update_cursor(crtc, true);
> @@ -4184,6 +4185,7 @@ static void i9xx_crtc_enable(struct drm_crtc *crtc)
>
>         intel_update_watermarks(crtc);
>         intel_enable_pipe(dev_priv, pipe, false, false);
> +       intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
>         intel_enable_primary_plane(dev_priv, plane, pipe);
>         intel_enable_planes(crtc);
>         /* The fixup needs to happen before cursor is enabled */
> @@ -4242,6 +4244,7 @@ static void i9xx_crtc_disable(struct drm_crtc *crtc)
>         intel_disable_planes(crtc);
>         intel_disable_primary_plane(dev_priv, plane, pipe);
>
> +       intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
>         intel_disable_pipe(dev_priv, pipe);
>
>         i9xx_pfit_disable(intel_crtc);
> --
> 1.8.3.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
Paulo Zanoni

[PATCH 2/3] drm/i915: Make underruns DRM_ERROR

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

I want to see these without having full debugs enabled.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c | 26 +++++++++++++-------------
 1 file changed, 13 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index e5cba0b..391cacd 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1472,7 +1472,7 @@ static irqreturn_t valleyview_irq_handler(int irq, void *arg)
 
 			if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
 			    intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
-				DRM_DEBUG_DRIVER("pipe %c underrun\n", pipe_name(pipe));
+				DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
 		}
 
 		/* Consume port.  Then clear IIR or we'll miss events */
@@ -1552,12 +1552,12 @@ static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
 	if (pch_iir & SDE_TRANSA_FIFO_UNDER)
 		if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
 							  false))
-			DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n");
+			DRM_ERROR("PCH transcoder A FIFO underrun\n");
 
 	if (pch_iir & SDE_TRANSB_FIFO_UNDER)
 		if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
 							  false))
-			DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n");
+			DRM_ERROR("PCH transcoder B FIFO underrun\n");
 }
 
 static void ivb_err_int_handler(struct drm_device *dev)
@@ -1573,8 +1573,8 @@ static void ivb_err_int_handler(struct drm_device *dev)
 		if (err_int & ERR_INT_FIFO_UNDERRUN(pipe)) {
 			if (intel_set_cpu_fifo_underrun_reporting(dev, pipe,
 								  false))
-				DRM_DEBUG_DRIVER("Pipe %c FIFO underrun\n",
-						 pipe_name(pipe));
+				DRM_ERROR("Pipe %c FIFO underrun\n",
+					  pipe_name(pipe));
 		}
 
 		if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) {
@@ -1599,17 +1599,17 @@ static void cpt_serr_int_handler(struct drm_device *dev)
 	if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
 		if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
 							  false))
-			DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n");
+			DRM_ERROR("PCH transcoder A FIFO underrun\n");
 
 	if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN)
 		if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
 							  false))
-			DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n");
+			DRM_ERROR("PCH transcoder B FIFO underrun\n");
 
 	if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN)
 		if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_C,
 							  false))
-			DRM_DEBUG_DRIVER("PCH transcoder C FIFO underrun\n");
+			DRM_ERROR("PCH transcoder C FIFO underrun\n");
 
 	I915_WRITE(SERR_INT, serr_int);
 }
@@ -1671,8 +1671,8 @@ static void ilk_display_irq_handler(struct drm_device *dev, u32 de_iir)
 
 		if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))
 			if (intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
-				DRM_DEBUG_DRIVER("Pipe %c FIFO underrun\n",
-						 pipe_name(pipe));
+				DRM_ERROR("Pipe %c FIFO underrun\n",
+					  pipe_name(pipe));
 
 		if (de_iir & DE_PIPE_CRC_DONE(pipe))
 			i9xx_pipe_crc_irq_handler(dev, pipe);
@@ -3229,7 +3229,7 @@ static irqreturn_t i8xx_irq_handler(int irq, void *arg)
 
 			if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
 			    intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
-				DRM_DEBUG_DRIVER("pipe %c underrun\n", pipe_name(pipe));
+				DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
 		}
 
 		iir = new_iir;
@@ -3430,7 +3430,7 @@ static irqreturn_t i915_irq_handler(int irq, void *arg)
 
 			if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
 			    intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
-				DRM_DEBUG_DRIVER("pipe %c underrun\n", pipe_name(pipe));
+				DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
 		}
 
 		if (blc_event || (iir & I915_ASLE_INTERRUPT))
@@ -3678,7 +3678,7 @@ static irqreturn_t i965_irq_handler(int irq, void *arg)
 
 			if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
 			    intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
-				DRM_DEBUG_DRIVER("pipe %c underrun\n", pipe_name(pipe));
+				DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
 		}
 
 		if (blc_event || (iir & I915_ASLE_INTERRUPT))
-- 
1.8.3.2

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 2/3] drm/i915: Make underruns DRM_ERROR

[Paulo Zanoni]

2014/1/17  <ville.syrjala@linux.intel.com>:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> I want to see these without having full debugs enabled.

You missed gen8_irq_handler().

With that fixed: Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>

I guess this could easily be done by Daniel when applying the patch.


>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_irq.c | 26 +++++++++++++-------------
>  1 file changed, 13 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index e5cba0b..391cacd 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -1472,7 +1472,7 @@ static irqreturn_t valleyview_irq_handler(int irq, void *arg)
>
>                         if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
>                             intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
> -                               DRM_DEBUG_DRIVER("pipe %c underrun\n", pipe_name(pipe));
> +                               DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
>                 }
>
>                 /* Consume port.  Then clear IIR or we'll miss events */
> @@ -1552,12 +1552,12 @@ static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
>         if (pch_iir & SDE_TRANSA_FIFO_UNDER)
>                 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
>                                                           false))
> -                       DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n");
> +                       DRM_ERROR("PCH transcoder A FIFO underrun\n");
>
>         if (pch_iir & SDE_TRANSB_FIFO_UNDER)
>                 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
>                                                           false))
> -                       DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n");
> +                       DRM_ERROR("PCH transcoder B FIFO underrun\n");
>  }
>
>  static void ivb_err_int_handler(struct drm_device *dev)
> @@ -1573,8 +1573,8 @@ static void ivb_err_int_handler(struct drm_device *dev)
>                 if (err_int & ERR_INT_FIFO_UNDERRUN(pipe)) {
>                         if (intel_set_cpu_fifo_underrun_reporting(dev, pipe,
>                                                                   false))
> -                               DRM_DEBUG_DRIVER("Pipe %c FIFO underrun\n",
> -                                                pipe_name(pipe));
> +                               DRM_ERROR("Pipe %c FIFO underrun\n",
> +                                         pipe_name(pipe));
>                 }
>
>                 if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) {
> @@ -1599,17 +1599,17 @@ static void cpt_serr_int_handler(struct drm_device *dev)
>         if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
>                 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
>                                                           false))
> -                       DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n");
> +                       DRM_ERROR("PCH transcoder A FIFO underrun\n");
>
>         if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN)
>                 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
>                                                           false))
> -                       DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n");
> +                       DRM_ERROR("PCH transcoder B FIFO underrun\n");
>
>         if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN)
>                 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_C,
>                                                           false))
> -                       DRM_DEBUG_DRIVER("PCH transcoder C FIFO underrun\n");
> +                       DRM_ERROR("PCH transcoder C FIFO underrun\n");
>
>         I915_WRITE(SERR_INT, serr_int);
>  }
> @@ -1671,8 +1671,8 @@ static void ilk_display_irq_handler(struct drm_device *dev, u32 de_iir)
>
>                 if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))
>                         if (intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
> -                               DRM_DEBUG_DRIVER("Pipe %c FIFO underrun\n",
> -                                                pipe_name(pipe));
> +                               DRM_ERROR("Pipe %c FIFO underrun\n",
> +                                         pipe_name(pipe));
>
>                 if (de_iir & DE_PIPE_CRC_DONE(pipe))
>                         i9xx_pipe_crc_irq_handler(dev, pipe);
> @@ -3229,7 +3229,7 @@ static irqreturn_t i8xx_irq_handler(int irq, void *arg)
>
>                         if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
>                             intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
> -                               DRM_DEBUG_DRIVER("pipe %c underrun\n", pipe_name(pipe));
> +                               DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
>                 }
>
>                 iir = new_iir;
> @@ -3430,7 +3430,7 @@ static irqreturn_t i915_irq_handler(int irq, void *arg)
>
>                         if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
>                             intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
> -                               DRM_DEBUG_DRIVER("pipe %c underrun\n", pipe_name(pipe));
> +                               DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
>                 }
>
>                 if (blc_event || (iir & I915_ASLE_INTERRUPT))
> @@ -3678,7 +3678,7 @@ static irqreturn_t i965_irq_handler(int irq, void *arg)
>
>                         if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
>                             intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
> -                               DRM_DEBUG_DRIVER("pipe %c underrun\n", pipe_name(pipe));
> +                               DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
>                 }
>
>                 if (blc_event || (iir & I915_ASLE_INTERRUPT))
> --
> 1.8.3.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
Paulo Zanoni

Re: [PATCH 2/3] drm/i915: Make underruns DRM_ERROR

[Daniel Vetter]

On Fri, Jan 24, 2014 at 04:42:55PM -0200, Paulo Zanoni wrote:
> 2014/1/17  <ville.syrjala@linux.intel.com>:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > I want to see these without having full debugs enabled.
> 
> You missed gen8_irq_handler().
> 
> With that fixed: Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> 
> I guess this could easily be done by Daniel when applying the patch.

Done so and applied patches 1&2 of this series, thanks.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

[PATCH 3/3] drm/i915: Re-enable underrun reporting after 2 secs

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

I'm interested in underruns so having the totally off is not good. After
disabling underruns, re-enable them after 2 seconds. I just added one
timer for this, even though we should have one for each PCH and CPU,
or maybe even per pipe/transcoder, but then we should track underrun
disable also per pipe/transcoder.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h |  1 +
 drivers/gpu/drm/i915/i915_irq.c | 29 +++++++++++++++++++++++++++++
 2 files changed, 30 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 283e875..0f4c346 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1419,6 +1419,7 @@ typedef struct drm_i915_private {
 	} hpd_stats[HPD_NUM_PINS];
 	u32 hpd_event_bits;
 	struct timer_list hotplug_reenable_timer;
+	struct timer_list underrun_reenable_timer;
 
 	int num_plane;
 
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 391cacd..849f4a6 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -416,6 +416,10 @@ bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
 
 done:
 	spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
+
+	if (!enable && ret)
+		mod_timer(&dev_priv->underrun_reenable_timer, jiffies + 2 * HZ);
+
 	return ret;
 }
 
@@ -468,9 +472,24 @@ bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev,
 
 done:
 	spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
+
+	if (!enable && ret)
+		mod_timer(&dev_priv->underrun_reenable_timer, jiffies + 2 * HZ);
+
 	return ret;
 }
 
+static void i915_underrun_reenable(unsigned long data)
+{
+	struct drm_device *dev = (struct drm_device *)data;
+	enum pipe pipe;
+
+	for_each_pipe(pipe) {
+		if (HAS_PCH_SPLIT(dev))
+			intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
+		intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
+	}
+}
 
 void
 i915_enable_pipestat(drm_i915_private_t *dev_priv, enum pipe pipe, u32 mask)
@@ -3003,6 +3022,7 @@ static void gen8_irq_uninstall(struct drm_device *dev)
 	if (!dev_priv)
 		return;
 
+	del_timer_sync(&dev_priv->underrun_reenable_timer);
 	del_timer_sync(&dev_priv->hotplug_reenable_timer);
 
 	I915_WRITE(GEN8_MASTER_IRQ, 0);
@@ -3045,6 +3065,7 @@ static void valleyview_irq_uninstall(struct drm_device *dev)
 	if (!dev_priv)
 		return;
 
+	del_timer_sync(&dev_priv->underrun_reenable_timer);
 	del_timer_sync(&dev_priv->hotplug_reenable_timer);
 
 	for_each_pipe(pipe)
@@ -3068,6 +3089,7 @@ static void ironlake_irq_uninstall(struct drm_device *dev)
 	if (!dev_priv)
 		return;
 
+	del_timer_sync(&dev_priv->underrun_reenable_timer);
 	del_timer_sync(&dev_priv->hotplug_reenable_timer);
 
 	I915_WRITE(HWSTAM, 0xffffffff);
@@ -3243,6 +3265,8 @@ static void i8xx_irq_uninstall(struct drm_device * dev)
 	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 	int pipe;
 
+	del_timer_sync(&dev_priv->underrun_reenable_timer);
+
 	for_each_pipe(pipe) {
 		/* Clear enable bits; then clear status bits */
 		I915_WRITE(PIPESTAT(pipe), 0);
@@ -3465,6 +3489,7 @@ static void i915_irq_uninstall(struct drm_device * dev)
 	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 	int pipe;
 
+	del_timer_sync(&dev_priv->underrun_reenable_timer);
 	del_timer_sync(&dev_priv->hotplug_reenable_timer);
 
 	if (I915_HAS_HOTPLUG(dev)) {
@@ -3718,6 +3743,7 @@ static void i965_irq_uninstall(struct drm_device * dev)
 	if (!dev_priv)
 		return;
 
+	del_timer_sync(&dev_priv->underrun_reenable_timer);
 	del_timer_sync(&dev_priv->hotplug_reenable_timer);
 
 	I915_WRITE(PORT_HOTPLUG_EN, 0);
@@ -3779,6 +3805,9 @@ void intel_irq_init(struct drm_device *dev)
 	INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
 	INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
 
+	setup_timer(&dev_priv->underrun_reenable_timer,
+		    i915_underrun_reenable,
+		    (unsigned long) dev);
 	setup_timer(&dev_priv->gpu_error.hangcheck_timer,
 		    i915_hangcheck_elapsed,
 		    (unsigned long) dev);
-- 
1.8.3.2

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 3/3] drm/i915: Re-enable underrun reporting after 2 secs

[Daniel Vetter]

On Fri, Jan 17, 2014 at 11:44:33AM +0200, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> I'm interested in underruns so having the totally off is not good. After
> disabling underruns, re-enable them after 2 seconds. I just added one
> timer for this, even though we should have one for each PCH and CPU,
> or maybe even per pipe/transcoder, but then we should track underrun
> disable also per pipe/transcoder.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

The kernel has some neat ratelimiting stuff in ratelimit.h. You've looked
into that? Open coding timer code always freaks me out a bit because of
the bazillion ways you can screw up jiffy handling ;-)
-Daniel

> ---
>  drivers/gpu/drm/i915/i915_drv.h |  1 +
>  drivers/gpu/drm/i915/i915_irq.c | 29 +++++++++++++++++++++++++++++
>  2 files changed, 30 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 283e875..0f4c346 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1419,6 +1419,7 @@ typedef struct drm_i915_private {
>  	} hpd_stats[HPD_NUM_PINS];
>  	u32 hpd_event_bits;
>  	struct timer_list hotplug_reenable_timer;
> +	struct timer_list underrun_reenable_timer;
>  
>  	int num_plane;
>  
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 391cacd..849f4a6 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -416,6 +416,10 @@ bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
>  
>  done:
>  	spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
> +
> +	if (!enable && ret)
> +		mod_timer(&dev_priv->underrun_reenable_timer, jiffies + 2 * HZ);
> +
>  	return ret;
>  }
>  
> @@ -468,9 +472,24 @@ bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev,
>  
>  done:
>  	spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
> +
> +	if (!enable && ret)
> +		mod_timer(&dev_priv->underrun_reenable_timer, jiffies + 2 * HZ);
> +
>  	return ret;
>  }
>  
> +static void i915_underrun_reenable(unsigned long data)
> +{
> +	struct drm_device *dev = (struct drm_device *)data;
> +	enum pipe pipe;
> +
> +	for_each_pipe(pipe) {
> +		if (HAS_PCH_SPLIT(dev))
> +			intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
> +		intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
> +	}
> +}
>  
>  void
>  i915_enable_pipestat(drm_i915_private_t *dev_priv, enum pipe pipe, u32 mask)
> @@ -3003,6 +3022,7 @@ static void gen8_irq_uninstall(struct drm_device *dev)
>  	if (!dev_priv)
>  		return;
>  
> +	del_timer_sync(&dev_priv->underrun_reenable_timer);
>  	del_timer_sync(&dev_priv->hotplug_reenable_timer);
>  
>  	I915_WRITE(GEN8_MASTER_IRQ, 0);
> @@ -3045,6 +3065,7 @@ static void valleyview_irq_uninstall(struct drm_device *dev)
>  	if (!dev_priv)
>  		return;
>  
> +	del_timer_sync(&dev_priv->underrun_reenable_timer);
>  	del_timer_sync(&dev_priv->hotplug_reenable_timer);
>  
>  	for_each_pipe(pipe)
> @@ -3068,6 +3089,7 @@ static void ironlake_irq_uninstall(struct drm_device *dev)
>  	if (!dev_priv)
>  		return;
>  
> +	del_timer_sync(&dev_priv->underrun_reenable_timer);
>  	del_timer_sync(&dev_priv->hotplug_reenable_timer);
>  
>  	I915_WRITE(HWSTAM, 0xffffffff);
> @@ -3243,6 +3265,8 @@ static void i8xx_irq_uninstall(struct drm_device * dev)
>  	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
>  	int pipe;
>  
> +	del_timer_sync(&dev_priv->underrun_reenable_timer);
> +
>  	for_each_pipe(pipe) {
>  		/* Clear enable bits; then clear status bits */
>  		I915_WRITE(PIPESTAT(pipe), 0);
> @@ -3465,6 +3489,7 @@ static void i915_irq_uninstall(struct drm_device * dev)
>  	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
>  	int pipe;
>  
> +	del_timer_sync(&dev_priv->underrun_reenable_timer);
>  	del_timer_sync(&dev_priv->hotplug_reenable_timer);
>  
>  	if (I915_HAS_HOTPLUG(dev)) {
> @@ -3718,6 +3743,7 @@ static void i965_irq_uninstall(struct drm_device * dev)
>  	if (!dev_priv)
>  		return;
>  
> +	del_timer_sync(&dev_priv->underrun_reenable_timer);
>  	del_timer_sync(&dev_priv->hotplug_reenable_timer);
>  
>  	I915_WRITE(PORT_HOTPLUG_EN, 0);
> @@ -3779,6 +3805,9 @@ void intel_irq_init(struct drm_device *dev)
>  	INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
>  	INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
>  
> +	setup_timer(&dev_priv->underrun_reenable_timer,
> +		    i915_underrun_reenable,
> +		    (unsigned long) dev);
>  	setup_timer(&dev_priv->gpu_error.hangcheck_timer,
>  		    i915_hangcheck_elapsed,
>  		    (unsigned long) dev);
> -- 
> 1.8.3.2
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH 3/3] drm/i915: Re-enable underrun reporting after 2 secs

[Ville Syrjälä]

On Fri, Jan 17, 2014 at 06:00:13PM +0100, Daniel Vetter wrote:
> On Fri, Jan 17, 2014 at 11:44:33AM +0200, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > I'm interested in underruns so having the totally off is not good. After
> > disabling underruns, re-enable them after 2 seconds. I just added one
> > timer for this, even though we should have one for each PCH and CPU,
> > or maybe even per pipe/transcoder, but then we should track underrun
> > disable also per pipe/transcoder.
> > 
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> The kernel has some neat ratelimiting stuff in ratelimit.h. You've looked
> into that? Open coding timer code always freaks me out a bit because of
> the bazillion ways you can screw up jiffy handling ;-)

Nope didn't really look. printk_timed_ratelimit() would seem like a
reasonable thing, except on PCH platforms we're also limiting the
interrupts themself, not just the printks. So using prink ratelimiting
can't give us quite the same thing.

-- 
Ville Syrjälä
Intel OTC