* [PATCH 1/2] drm/i915: clock readout support for DDI v2
@ 2014-01-20 22:18 Jesse Barnes
2014-01-20 22:18 ` [PATCH 2/2] drm/i915: always check clocks when comparing pipe configs Jesse Barnes
2014-01-21 11:36 ` [PATCH 1/2] drm/i915: clock readout support for DDI v2 Ville Syrjälä
0 siblings, 2 replies; 7+ messages in thread
From: Jesse Barnes @ 2014-01-20 22:18 UTC (permalink / raw)
To: intel-gfx
Read out and calculate the port and pixel clocks on DDI configs as well.
This means we have to grab the DP divider values and look at the port
mapping to figure out which clock select reg to read out.
v2: do the work from ddi_get_config (Ville)
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
drivers/gpu/drm/i915/i915_reg.h | 6 ++++
drivers/gpu/drm/i915/intel_ddi.c | 61 ++++++++++++++++++++++++++++++++++++
drivers/gpu/drm/i915/intel_display.c | 2 ++
3 files changed, 69 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a699efd..644e4f9 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5318,8 +5318,13 @@
#define WRPLL_PLL_SELECT_LCPLL_2700 (0x03<<28)
/* WRPLL divider programming */
#define WRPLL_DIVIDER_REFERENCE(x) ((x)<<0)
+#define WRPLL_DIVIDER_REF_MASK (0xff)
#define WRPLL_DIVIDER_POST(x) ((x)<<8)
+#define WRPLL_DIVIDER_POST_MASK (0x3f<<8)
+#define WRPLL_DIVIDER_POST_SHIFT 8
#define WRPLL_DIVIDER_FEEDBACK(x) ((x)<<16)
+#define WRPLL_DIVIDER_FB_SHIFT 16
+#define WRPLL_DIVIDER_FB_MASK (0xff<<16)
/* Port clock selection */
#define PORT_CLK_SEL_A 0x46100
@@ -5332,6 +5337,7 @@
#define PORT_CLK_SEL_WRPLL1 (4<<29)
#define PORT_CLK_SEL_WRPLL2 (5<<29)
#define PORT_CLK_SEL_NONE (7<<29)
+#define PORT_CLK_SEL_MASK (7<<29)
/* Transcoder clock selection */
#define TRANS_CLK_SEL_A 0x46140
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 1488b28..d836c16 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -633,6 +633,65 @@ static void wrpll_update_rnp(uint64_t freq2k, unsigned budget,
/* Otherwise a < c && b >= d, do nothing */
}
+static int intel_ddi_calc_wrpll_link(u32 wrpll)
+{
+ int n, p, r;
+
+ r = wrpll & WRPLL_DIVIDER_REF_MASK;
+ p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
+ n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
+
+ return (LC_FREQ * n) / (p * r);
+}
+
+static void haswell_ddi_clock_get(struct intel_encoder *encoder,
+ struct intel_crtc_config *pipe_config)
+{
+ struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
+ enum port port = intel_ddi_get_encoder_port(encoder);
+ int link_clock;
+ u32 val, pll;
+
+ val = I915_READ(PORT_CLK_SEL(port));
+ switch (val & PORT_CLK_SEL_MASK) {
+ case PORT_CLK_SEL_LCPLL_810:
+ link_clock = 81000;
+ break;
+ case PORT_CLK_SEL_LCPLL_1350:
+ link_clock = 135000;
+ break;
+ case PORT_CLK_SEL_LCPLL_2700:
+ link_clock = 270000;
+ break;
+ case PORT_CLK_SEL_WRPLL1:
+ pll = I915_READ(WRPLL_CTL1);
+ link_clock = intel_ddi_calc_wrpll_link(pll);
+ break;
+ case PORT_CLK_SEL_WRPLL2:
+ pll = I915_READ(WRPLL_CTL2);
+ link_clock = intel_ddi_calc_wrpll_link(pll);
+ break;
+ case PORT_CLK_SEL_SPLL:
+ link_clock = 135000;
+ break;
+ default:
+ WARN(1, "bad port clock sel\n");
+ return;
+ }
+
+ if (pipe_config->has_pch_encoder)
+ pipe_config->adjusted_mode.crtc_clock =
+ intel_dotclock_calculate(link_clock,
+ &pipe_config->fdi_m_n);
+ else
+ pipe_config->adjusted_mode.crtc_clock =
+ intel_dotclock_calculate(link_clock,
+ &pipe_config->dp_m_n);
+
+ pipe_config->port_clock = link_clock * 2;
+ pipe_config->adjusted_mode.crtc_clock *= 2;
+}
+
static void
intel_ddi_calculate_wrpll(int clock /* in Hz */,
unsigned *r2_out, unsigned *n2_out, unsigned *p_out)
@@ -1504,6 +1563,8 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
}
+
+ haswell_ddi_clock_get(encoder, pipe_config);
}
static void intel_ddi_destroy(struct drm_encoder *encoder)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 74137d5..40e5252 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6998,6 +6998,8 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
ironlake_get_fdi_m_n_config(crtc, pipe_config);
}
+ intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
+ &pipe_config->dp_m_n);
intel_get_pipe_timings(crtc, pipe_config);
pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
--
1.8.3.2
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 2/2] drm/i915: always check clocks when comparing pipe configs
2014-01-20 22:18 [PATCH 1/2] drm/i915: clock readout support for DDI v2 Jesse Barnes
@ 2014-01-20 22:18 ` Jesse Barnes
2014-01-21 11:36 ` [PATCH 1/2] drm/i915: clock readout support for DDI v2 Ville Syrjälä
1 sibling, 0 replies; 7+ messages in thread
From: Jesse Barnes @ 2014-01-20 22:18 UTC (permalink / raw)
To: intel-gfx
Now that we have DDI support, we can check these all the time.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
drivers/gpu/drm/i915/intel_display.c | 6 ++----
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 40e5252..8bd8279 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -9353,10 +9353,8 @@ intel_pipe_config_compare(struct drm_device *dev,
if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
PIPE_CONF_CHECK_I(pipe_bpp);
- if (!HAS_DDI(dev)) {
- PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
- PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
- }
+ PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
+ PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
#undef PIPE_CONF_CHECK_X
#undef PIPE_CONF_CHECK_I
--
1.8.3.2
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH 1/2] drm/i915: clock readout support for DDI v2
2014-01-20 22:18 [PATCH 1/2] drm/i915: clock readout support for DDI v2 Jesse Barnes
2014-01-20 22:18 ` [PATCH 2/2] drm/i915: always check clocks when comparing pipe configs Jesse Barnes
@ 2014-01-21 11:36 ` Ville Syrjälä
2014-01-21 20:38 ` Jesse Barnes
2014-01-21 20:42 ` [PATCH] drm/i915: clock readout support for DDI v3 Jesse Barnes
1 sibling, 2 replies; 7+ messages in thread
From: Ville Syrjälä @ 2014-01-21 11:36 UTC (permalink / raw)
To: Jesse Barnes; +Cc: intel-gfx
On Mon, Jan 20, 2014 at 02:18:03PM -0800, Jesse Barnes wrote:
> Read out and calculate the port and pixel clocks on DDI configs as well.
> This means we have to grab the DP divider values and look at the port
> mapping to figure out which clock select reg to read out.
>
> v2: do the work from ddi_get_config (Ville)
>
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 6 ++++
> drivers/gpu/drm/i915/intel_ddi.c | 61 ++++++++++++++++++++++++++++++++++++
> drivers/gpu/drm/i915/intel_display.c | 2 ++
> 3 files changed, 69 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index a699efd..644e4f9 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5318,8 +5318,13 @@
> #define WRPLL_PLL_SELECT_LCPLL_2700 (0x03<<28)
> /* WRPLL divider programming */
> #define WRPLL_DIVIDER_REFERENCE(x) ((x)<<0)
> +#define WRPLL_DIVIDER_REF_MASK (0xff)
> #define WRPLL_DIVIDER_POST(x) ((x)<<8)
> +#define WRPLL_DIVIDER_POST_MASK (0x3f<<8)
> +#define WRPLL_DIVIDER_POST_SHIFT 8
> #define WRPLL_DIVIDER_FEEDBACK(x) ((x)<<16)
> +#define WRPLL_DIVIDER_FB_SHIFT 16
> +#define WRPLL_DIVIDER_FB_MASK (0xff<<16)
>
> /* Port clock selection */
> #define PORT_CLK_SEL_A 0x46100
> @@ -5332,6 +5337,7 @@
> #define PORT_CLK_SEL_WRPLL1 (4<<29)
> #define PORT_CLK_SEL_WRPLL2 (5<<29)
> #define PORT_CLK_SEL_NONE (7<<29)
> +#define PORT_CLK_SEL_MASK (7<<29)
>
> /* Transcoder clock selection */
> #define TRANS_CLK_SEL_A 0x46140
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 1488b28..d836c16 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -633,6 +633,65 @@ static void wrpll_update_rnp(uint64_t freq2k, unsigned budget,
> /* Otherwise a < c && b >= d, do nothing */
> }
>
> +static int intel_ddi_calc_wrpll_link(u32 wrpll)
> +{
> + int n, p, r;
> +
> + r = wrpll & WRPLL_DIVIDER_REF_MASK;
> + p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
> + n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
> +
> + return (LC_FREQ * n) / (p * r);
This is assuming the WRPLL will use the LCPLL as reference. Ideally we
should read out the ref clock settings too.
> +}
> +
> +static void haswell_ddi_clock_get(struct intel_encoder *encoder,
> + struct intel_crtc_config *pipe_config)
> +{
> + struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
> + enum port port = intel_ddi_get_encoder_port(encoder);
> + int link_clock;
> + u32 val, pll;
> +
> + val = I915_READ(PORT_CLK_SEL(port));
> + switch (val & PORT_CLK_SEL_MASK) {
> + case PORT_CLK_SEL_LCPLL_810:
> + link_clock = 81000;
> + break;
> + case PORT_CLK_SEL_LCPLL_1350:
> + link_clock = 135000;
> + break;
> + case PORT_CLK_SEL_LCPLL_2700:
> + link_clock = 270000;
> + break;
> + case PORT_CLK_SEL_WRPLL1:
> + pll = I915_READ(WRPLL_CTL1);
> + link_clock = intel_ddi_calc_wrpll_link(pll);
> + break;
> + case PORT_CLK_SEL_WRPLL2:
> + pll = I915_READ(WRPLL_CTL2);
> + link_clock = intel_ddi_calc_wrpll_link(pll);
> + break;
> + case PORT_CLK_SEL_SPLL:
> + link_clock = 135000;
SPLL could also output 810 MHz.
> + break;
> + default:
> + WARN(1, "bad port clock sel\n");
> + return;
> + }
Could do the port_clock = link_clock * 2; here, and then pass port clock
to intel_dotclock_calculate() and avoid having to multiply crtc_clock by
2 afterwards.
As a side note, I must say it's a bit annoying that the DDI PLL code is
different to the rest of our PLL code. Hz vs. kHz etc. Makes it a bit
harder to figure out what it's doing.
> +
> + if (pipe_config->has_pch_encoder)
> + pipe_config->adjusted_mode.crtc_clock =
> + intel_dotclock_calculate(link_clock,
> + &pipe_config->fdi_m_n);
> + else
else if (has_dp_encoder)
> + pipe_config->adjusted_mode.crtc_clock =
> + intel_dotclock_calculate(link_clock,
> + &pipe_config->dp_m_n);
else
.crtc_clock = link_clock; // or port_clock if you take my suggestion above
> +
> + pipe_config->port_clock = link_clock * 2;
> + pipe_config->adjusted_mode.crtc_clock *= 2;
> +}
> +
> static void
> intel_ddi_calculate_wrpll(int clock /* in Hz */,
> unsigned *r2_out, unsigned *n2_out, unsigned *p_out)
> @@ -1504,6 +1563,8 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
> pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
> dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
> }
> +
> + haswell_ddi_clock_get(encoder, pipe_config);
> }
>
> static void intel_ddi_destroy(struct drm_encoder *encoder)
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 74137d5..40e5252 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -6998,6 +6998,8 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
> ironlake_get_fdi_m_n_config(crtc, pipe_config);
> }
>
> + intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
> + &pipe_config->dp_m_n);
Not needed. We already do intel_dp_get_m_n() in intel_ddi_get_config().
> intel_get_pipe_timings(crtc, pipe_config);
>
> pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
> --
> 1.8.3.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 1/2] drm/i915: clock readout support for DDI v2
2014-01-21 11:36 ` [PATCH 1/2] drm/i915: clock readout support for DDI v2 Ville Syrjälä
@ 2014-01-21 20:38 ` Jesse Barnes
2014-01-21 20:42 ` [PATCH] drm/i915: clock readout support for DDI v3 Jesse Barnes
1 sibling, 0 replies; 7+ messages in thread
From: Jesse Barnes @ 2014-01-21 20:38 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Tue, 21 Jan 2014 13:36:56 +0200
Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> > +static int intel_ddi_calc_wrpll_link(u32 wrpll)
> > +{
> > + int n, p, r;
> > +
> > + r = wrpll & WRPLL_DIVIDER_REF_MASK;
> > + p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
> > + n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
> > +
> > + return (LC_FREQ * n) / (p * r);
>
> This is assuming the WRPLL will use the LCPLL as reference. Ideally we
> should read out the ref clock settings too.
I don't think I see that in this config, but I've added code to look
for that. Not sure if I got the ref freq right either; I think it's
135MHz in the PCH case...
> > + case PORT_CLK_SEL_SPLL:
> > + link_clock = 135000;
>
> SPLL could also output 810 MHz.
And even 2700 MHz. Fixed.
> > + break;
> > + default:
> > + WARN(1, "bad port clock sel\n");
> > + return;
> > + }
>
> Could do the port_clock = link_clock * 2; here, and then pass port clock
> to intel_dotclock_calculate() and avoid having to multiply crtc_clock by
> 2 afterwards.
Yeah that tidies things up nicely. Fixed.
> As a side note, I must say it's a bit annoying that the DDI PLL code is
> different to the rest of our PLL code. Hz vs. kHz etc. Makes it a bit
> harder to figure out what it's doing.
Yeah that could be converted, mixing them up definitely isn't ideal.
> > +
> > + if (pipe_config->has_pch_encoder)
> > + pipe_config->adjusted_mode.crtc_clock =
> > + intel_dotclock_calculate(link_clock,
> > + &pipe_config->fdi_m_n);
> > + else
>
> else if (has_dp_encoder)
>
> > + pipe_config->adjusted_mode.crtc_clock =
> > + intel_dotclock_calculate(link_clock,
> > + &pipe_config->dp_m_n);
>
> else
> .crtc_clock = link_clock; // or port_clock if you take my suggestion above
Fixed.
> > + intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
> > + &pipe_config->dp_m_n);
>
> Not needed. We already do intel_dp_get_m_n() in intel_ddi_get_config().
Ah right, just above. Fixed.
Thanks a lot for the review.
--
Jesse Barnes, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH] drm/i915: clock readout support for DDI v3
2014-01-21 11:36 ` [PATCH 1/2] drm/i915: clock readout support for DDI v2 Ville Syrjälä
2014-01-21 20:38 ` Jesse Barnes
@ 2014-01-21 20:42 ` Jesse Barnes
2014-01-22 8:56 ` Ville Syrjälä
1 sibling, 1 reply; 7+ messages in thread
From: Jesse Barnes @ 2014-01-21 20:42 UTC (permalink / raw)
To: intel-gfx
Read out and calculate the port and pixel clocks on DDI configs as well.
This means we have to grab the DP divider values and look at the port
mapping to figure out which clock select reg to read out.
v2: do the work from ddi_get_config (Ville)
v3: check WRPLL reference clock (Ville)
add additional SPLL freqs (Ville)
clean up port/crtc clock calc (Ville)
fix up crtc_clock conditionals (Ville)
drop superfluous dp_get_m_n from get_config (Ville)
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
drivers/gpu/drm/i915/i915_reg.h | 10 +++++
drivers/gpu/drm/i915/intel_ddi.c | 92 ++++++++++++++++++++++++++++++++++++++++
2 files changed, 102 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a699efd..7bfc710 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5306,8 +5306,12 @@
#define SPLL_PLL_ENABLE (1<<31)
#define SPLL_PLL_SSC (1<<28)
#define SPLL_PLL_NON_SSC (2<<28)
+#define SPLL_PLL_LCPLL (3<<28)
+#define SPLL_PLL_REF_MASK (3<<28)
#define SPLL_PLL_FREQ_810MHz (0<<26)
#define SPLL_PLL_FREQ_1350MHz (1<<26)
+#define SPLL_PLL_FREQ_2700MHz (2<<26)
+#define SPLL_PLL_FREQ_MASK (3<<26)
/* WRPLL */
#define WRPLL_CTL1 0x46040
@@ -5318,8 +5322,13 @@
#define WRPLL_PLL_SELECT_LCPLL_2700 (0x03<<28)
/* WRPLL divider programming */
#define WRPLL_DIVIDER_REFERENCE(x) ((x)<<0)
+#define WRPLL_DIVIDER_REF_MASK (0xff)
#define WRPLL_DIVIDER_POST(x) ((x)<<8)
+#define WRPLL_DIVIDER_POST_MASK (0x3f<<8)
+#define WRPLL_DIVIDER_POST_SHIFT 8
#define WRPLL_DIVIDER_FEEDBACK(x) ((x)<<16)
+#define WRPLL_DIVIDER_FB_SHIFT 16
+#define WRPLL_DIVIDER_FB_MASK (0xff<<16)
/* Port clock selection */
#define PORT_CLK_SEL_A 0x46100
@@ -5332,6 +5341,7 @@
#define PORT_CLK_SEL_WRPLL1 (4<<29)
#define PORT_CLK_SEL_WRPLL2 (5<<29)
#define PORT_CLK_SEL_NONE (7<<29)
+#define PORT_CLK_SEL_MASK (7<<29)
/* Transcoder clock selection */
#define TRANS_CLK_SEL_A 0x46140
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 1488b28..b6171cf 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -633,6 +633,96 @@ static void wrpll_update_rnp(uint64_t freq2k, unsigned budget,
/* Otherwise a < c && b >= d, do nothing */
}
+static int intel_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
+ int reg)
+{
+ int refclk = LC_FREQ;
+ int n, p, r;
+ u32 wrpll;
+
+ wrpll = I915_READ(reg);
+ switch (wrpll & SPLL_PLL_REF_MASK) {
+ case SPLL_PLL_SSC:
+ case SPLL_PLL_NON_SSC:
+ /*
+ * We could calculate spread here, but our checking
+ * code only cares about 5% accuracy, and spread is a max of
+ * 0.5% downspread.
+ */
+ refclk = 135;
+ break;
+ case SPLL_PLL_LCPLL:
+ refclk = LC_FREQ;
+ break;
+ default:
+ WARN(1, "bad wrpll refclk\n");
+ return 0;
+ }
+
+ r = wrpll & WRPLL_DIVIDER_REF_MASK;
+ p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
+ n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
+
+ return (LC_FREQ * n) / (p * r);
+}
+
+static void intel_ddi_clock_get(struct intel_encoder *encoder,
+ struct intel_crtc_config *pipe_config)
+{
+ struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
+ enum port port = intel_ddi_get_encoder_port(encoder);
+ int link_clock = 0;
+ u32 val, pll;
+
+ val = I915_READ(PORT_CLK_SEL(port));
+ switch (val & PORT_CLK_SEL_MASK) {
+ case PORT_CLK_SEL_LCPLL_810:
+ link_clock = 81000;
+ break;
+ case PORT_CLK_SEL_LCPLL_1350:
+ link_clock = 135000;
+ break;
+ case PORT_CLK_SEL_LCPLL_2700:
+ link_clock = 270000;
+ break;
+ case PORT_CLK_SEL_WRPLL1:
+ link_clock = intel_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL1);
+ break;
+ case PORT_CLK_SEL_WRPLL2:
+ link_clock = intel_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL2);
+ break;
+ case PORT_CLK_SEL_SPLL:
+ pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
+ if (pll == SPLL_PLL_FREQ_810MHz)
+ link_clock = 81000;
+ else if (pll == SPLL_PLL_FREQ_1350MHz)
+ link_clock = 135000;
+ else if (pll == SPLL_PLL_FREQ_2700MHz)
+ link_clock = 270000;
+ else {
+ WARN(1, "bad spll freq\n");
+ return;
+ }
+ break;
+ default:
+ WARN(1, "bad port clock sel\n");
+ return;
+ }
+
+ pipe_config->port_clock = link_clock * 2;
+
+ if (pipe_config->has_pch_encoder)
+ pipe_config->adjusted_mode.crtc_clock =
+ intel_dotclock_calculate(pipe_config->port_clock,
+ &pipe_config->fdi_m_n);
+ else if (pipe_config->has_dp_encoder)
+ pipe_config->adjusted_mode.crtc_clock =
+ intel_dotclock_calculate(pipe_config->port_clock,
+ &pipe_config->dp_m_n);
+ else
+ pipe_config->adjusted_mode.crtc_clock = pipe_config->port_clock;
+}
+
static void
intel_ddi_calculate_wrpll(int clock /* in Hz */,
unsigned *r2_out, unsigned *n2_out, unsigned *p_out)
@@ -1504,6 +1594,8 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
}
+
+ intel_ddi_clock_get(encoder, pipe_config);
}
static void intel_ddi_destroy(struct drm_encoder *encoder)
--
1.8.3.2
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH] drm/i915: clock readout support for DDI v3
2014-01-21 20:42 ` [PATCH] drm/i915: clock readout support for DDI v3 Jesse Barnes
@ 2014-01-22 8:56 ` Ville Syrjälä
2014-01-22 9:46 ` Daniel Vetter
0 siblings, 1 reply; 7+ messages in thread
From: Ville Syrjälä @ 2014-01-22 8:56 UTC (permalink / raw)
To: Jesse Barnes; +Cc: intel-gfx
On Tue, Jan 21, 2014 at 12:42:10PM -0800, Jesse Barnes wrote:
> Read out and calculate the port and pixel clocks on DDI configs as well.
> This means we have to grab the DP divider values and look at the port
> mapping to figure out which clock select reg to read out.
>
> v2: do the work from ddi_get_config (Ville)
> v3: check WRPLL reference clock (Ville)
> add additional SPLL freqs (Ville)
> clean up port/crtc clock calc (Ville)
> fix up crtc_clock conditionals (Ville)
> drop superfluous dp_get_m_n from get_config (Ville)
>
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Look good.
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 10 +++++
> drivers/gpu/drm/i915/intel_ddi.c | 92 ++++++++++++++++++++++++++++++++++++++++
> 2 files changed, 102 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index a699efd..7bfc710 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5306,8 +5306,12 @@
> #define SPLL_PLL_ENABLE (1<<31)
> #define SPLL_PLL_SSC (1<<28)
> #define SPLL_PLL_NON_SSC (2<<28)
> +#define SPLL_PLL_LCPLL (3<<28)
> +#define SPLL_PLL_REF_MASK (3<<28)
> #define SPLL_PLL_FREQ_810MHz (0<<26)
> #define SPLL_PLL_FREQ_1350MHz (1<<26)
> +#define SPLL_PLL_FREQ_2700MHz (2<<26)
> +#define SPLL_PLL_FREQ_MASK (3<<26)
>
> /* WRPLL */
> #define WRPLL_CTL1 0x46040
> @@ -5318,8 +5322,13 @@
> #define WRPLL_PLL_SELECT_LCPLL_2700 (0x03<<28)
> /* WRPLL divider programming */
> #define WRPLL_DIVIDER_REFERENCE(x) ((x)<<0)
> +#define WRPLL_DIVIDER_REF_MASK (0xff)
> #define WRPLL_DIVIDER_POST(x) ((x)<<8)
> +#define WRPLL_DIVIDER_POST_MASK (0x3f<<8)
> +#define WRPLL_DIVIDER_POST_SHIFT 8
> #define WRPLL_DIVIDER_FEEDBACK(x) ((x)<<16)
> +#define WRPLL_DIVIDER_FB_SHIFT 16
> +#define WRPLL_DIVIDER_FB_MASK (0xff<<16)
>
> /* Port clock selection */
> #define PORT_CLK_SEL_A 0x46100
> @@ -5332,6 +5341,7 @@
> #define PORT_CLK_SEL_WRPLL1 (4<<29)
> #define PORT_CLK_SEL_WRPLL2 (5<<29)
> #define PORT_CLK_SEL_NONE (7<<29)
> +#define PORT_CLK_SEL_MASK (7<<29)
>
> /* Transcoder clock selection */
> #define TRANS_CLK_SEL_A 0x46140
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 1488b28..b6171cf 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -633,6 +633,96 @@ static void wrpll_update_rnp(uint64_t freq2k, unsigned budget,
> /* Otherwise a < c && b >= d, do nothing */
> }
>
> +static int intel_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
> + int reg)
> +{
> + int refclk = LC_FREQ;
> + int n, p, r;
> + u32 wrpll;
> +
> + wrpll = I915_READ(reg);
> + switch (wrpll & SPLL_PLL_REF_MASK) {
> + case SPLL_PLL_SSC:
> + case SPLL_PLL_NON_SSC:
> + /*
> + * We could calculate spread here, but our checking
> + * code only cares about 5% accuracy, and spread is a max of
> + * 0.5% downspread.
> + */
> + refclk = 135;
> + break;
> + case SPLL_PLL_LCPLL:
> + refclk = LC_FREQ;
> + break;
> + default:
> + WARN(1, "bad wrpll refclk\n");
> + return 0;
> + }
> +
> + r = wrpll & WRPLL_DIVIDER_REF_MASK;
> + p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
> + n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
> +
> + return (LC_FREQ * n) / (p * r);
> +}
> +
> +static void intel_ddi_clock_get(struct intel_encoder *encoder,
> + struct intel_crtc_config *pipe_config)
> +{
> + struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
> + enum port port = intel_ddi_get_encoder_port(encoder);
> + int link_clock = 0;
> + u32 val, pll;
> +
> + val = I915_READ(PORT_CLK_SEL(port));
> + switch (val & PORT_CLK_SEL_MASK) {
> + case PORT_CLK_SEL_LCPLL_810:
> + link_clock = 81000;
> + break;
> + case PORT_CLK_SEL_LCPLL_1350:
> + link_clock = 135000;
> + break;
> + case PORT_CLK_SEL_LCPLL_2700:
> + link_clock = 270000;
> + break;
> + case PORT_CLK_SEL_WRPLL1:
> + link_clock = intel_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL1);
> + break;
> + case PORT_CLK_SEL_WRPLL2:
> + link_clock = intel_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL2);
> + break;
> + case PORT_CLK_SEL_SPLL:
> + pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
> + if (pll == SPLL_PLL_FREQ_810MHz)
> + link_clock = 81000;
> + else if (pll == SPLL_PLL_FREQ_1350MHz)
> + link_clock = 135000;
> + else if (pll == SPLL_PLL_FREQ_2700MHz)
> + link_clock = 270000;
> + else {
> + WARN(1, "bad spll freq\n");
> + return;
> + }
> + break;
> + default:
> + WARN(1, "bad port clock sel\n");
> + return;
> + }
> +
> + pipe_config->port_clock = link_clock * 2;
> +
> + if (pipe_config->has_pch_encoder)
> + pipe_config->adjusted_mode.crtc_clock =
> + intel_dotclock_calculate(pipe_config->port_clock,
> + &pipe_config->fdi_m_n);
> + else if (pipe_config->has_dp_encoder)
> + pipe_config->adjusted_mode.crtc_clock =
> + intel_dotclock_calculate(pipe_config->port_clock,
> + &pipe_config->dp_m_n);
> + else
> + pipe_config->adjusted_mode.crtc_clock = pipe_config->port_clock;
> +}
> +
> static void
> intel_ddi_calculate_wrpll(int clock /* in Hz */,
> unsigned *r2_out, unsigned *n2_out, unsigned *p_out)
> @@ -1504,6 +1594,8 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
> pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
> dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
> }
> +
> + intel_ddi_clock_get(encoder, pipe_config);
> }
>
> static void intel_ddi_destroy(struct drm_encoder *encoder)
> --
> 1.8.3.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH] drm/i915: clock readout support for DDI v3
2014-01-22 8:56 ` Ville Syrjälä
@ 2014-01-22 9:46 ` Daniel Vetter
0 siblings, 0 replies; 7+ messages in thread
From: Daniel Vetter @ 2014-01-22 9:46 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Wed, Jan 22, 2014 at 10:56:36AM +0200, Ville Syrjälä wrote:
> On Tue, Jan 21, 2014 at 12:42:10PM -0800, Jesse Barnes wrote:
> > Read out and calculate the port and pixel clocks on DDI configs as well.
> > This means we have to grab the DP divider values and look at the port
> > mapping to figure out which clock select reg to read out.
> >
> > v2: do the work from ddi_get_config (Ville)
> > v3: check WRPLL reference clock (Ville)
> > add additional SPLL freqs (Ville)
> > clean up port/crtc clock calc (Ville)
> > fix up crtc_clock conditionals (Ville)
> > drop superfluous dp_get_m_n from get_config (Ville)
> >
> > Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
>
> Look good.
>
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Yay!
Both patches merged to dinq, thanks.
-Daniel
>
> > ---
> > drivers/gpu/drm/i915/i915_reg.h | 10 +++++
> > drivers/gpu/drm/i915/intel_ddi.c | 92 ++++++++++++++++++++++++++++++++++++++++
> > 2 files changed, 102 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index a699efd..7bfc710 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -5306,8 +5306,12 @@
> > #define SPLL_PLL_ENABLE (1<<31)
> > #define SPLL_PLL_SSC (1<<28)
> > #define SPLL_PLL_NON_SSC (2<<28)
> > +#define SPLL_PLL_LCPLL (3<<28)
> > +#define SPLL_PLL_REF_MASK (3<<28)
> > #define SPLL_PLL_FREQ_810MHz (0<<26)
> > #define SPLL_PLL_FREQ_1350MHz (1<<26)
> > +#define SPLL_PLL_FREQ_2700MHz (2<<26)
> > +#define SPLL_PLL_FREQ_MASK (3<<26)
> >
> > /* WRPLL */
> > #define WRPLL_CTL1 0x46040
> > @@ -5318,8 +5322,13 @@
> > #define WRPLL_PLL_SELECT_LCPLL_2700 (0x03<<28)
> > /* WRPLL divider programming */
> > #define WRPLL_DIVIDER_REFERENCE(x) ((x)<<0)
> > +#define WRPLL_DIVIDER_REF_MASK (0xff)
> > #define WRPLL_DIVIDER_POST(x) ((x)<<8)
> > +#define WRPLL_DIVIDER_POST_MASK (0x3f<<8)
> > +#define WRPLL_DIVIDER_POST_SHIFT 8
> > #define WRPLL_DIVIDER_FEEDBACK(x) ((x)<<16)
> > +#define WRPLL_DIVIDER_FB_SHIFT 16
> > +#define WRPLL_DIVIDER_FB_MASK (0xff<<16)
> >
> > /* Port clock selection */
> > #define PORT_CLK_SEL_A 0x46100
> > @@ -5332,6 +5341,7 @@
> > #define PORT_CLK_SEL_WRPLL1 (4<<29)
> > #define PORT_CLK_SEL_WRPLL2 (5<<29)
> > #define PORT_CLK_SEL_NONE (7<<29)
> > +#define PORT_CLK_SEL_MASK (7<<29)
> >
> > /* Transcoder clock selection */
> > #define TRANS_CLK_SEL_A 0x46140
> > diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> > index 1488b28..b6171cf 100644
> > --- a/drivers/gpu/drm/i915/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/intel_ddi.c
> > @@ -633,6 +633,96 @@ static void wrpll_update_rnp(uint64_t freq2k, unsigned budget,
> > /* Otherwise a < c && b >= d, do nothing */
> > }
> >
> > +static int intel_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
> > + int reg)
> > +{
> > + int refclk = LC_FREQ;
> > + int n, p, r;
> > + u32 wrpll;
> > +
> > + wrpll = I915_READ(reg);
> > + switch (wrpll & SPLL_PLL_REF_MASK) {
> > + case SPLL_PLL_SSC:
> > + case SPLL_PLL_NON_SSC:
> > + /*
> > + * We could calculate spread here, but our checking
> > + * code only cares about 5% accuracy, and spread is a max of
> > + * 0.5% downspread.
> > + */
> > + refclk = 135;
> > + break;
> > + case SPLL_PLL_LCPLL:
> > + refclk = LC_FREQ;
> > + break;
> > + default:
> > + WARN(1, "bad wrpll refclk\n");
> > + return 0;
> > + }
> > +
> > + r = wrpll & WRPLL_DIVIDER_REF_MASK;
> > + p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
> > + n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
> > +
> > + return (LC_FREQ * n) / (p * r);
> > +}
> > +
> > +static void intel_ddi_clock_get(struct intel_encoder *encoder,
> > + struct intel_crtc_config *pipe_config)
> > +{
> > + struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
> > + enum port port = intel_ddi_get_encoder_port(encoder);
> > + int link_clock = 0;
> > + u32 val, pll;
> > +
> > + val = I915_READ(PORT_CLK_SEL(port));
> > + switch (val & PORT_CLK_SEL_MASK) {
> > + case PORT_CLK_SEL_LCPLL_810:
> > + link_clock = 81000;
> > + break;
> > + case PORT_CLK_SEL_LCPLL_1350:
> > + link_clock = 135000;
> > + break;
> > + case PORT_CLK_SEL_LCPLL_2700:
> > + link_clock = 270000;
> > + break;
> > + case PORT_CLK_SEL_WRPLL1:
> > + link_clock = intel_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL1);
> > + break;
> > + case PORT_CLK_SEL_WRPLL2:
> > + link_clock = intel_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL2);
> > + break;
> > + case PORT_CLK_SEL_SPLL:
> > + pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
> > + if (pll == SPLL_PLL_FREQ_810MHz)
> > + link_clock = 81000;
> > + else if (pll == SPLL_PLL_FREQ_1350MHz)
> > + link_clock = 135000;
> > + else if (pll == SPLL_PLL_FREQ_2700MHz)
> > + link_clock = 270000;
> > + else {
> > + WARN(1, "bad spll freq\n");
> > + return;
> > + }
> > + break;
> > + default:
> > + WARN(1, "bad port clock sel\n");
> > + return;
> > + }
> > +
> > + pipe_config->port_clock = link_clock * 2;
> > +
> > + if (pipe_config->has_pch_encoder)
> > + pipe_config->adjusted_mode.crtc_clock =
> > + intel_dotclock_calculate(pipe_config->port_clock,
> > + &pipe_config->fdi_m_n);
> > + else if (pipe_config->has_dp_encoder)
> > + pipe_config->adjusted_mode.crtc_clock =
> > + intel_dotclock_calculate(pipe_config->port_clock,
> > + &pipe_config->dp_m_n);
> > + else
> > + pipe_config->adjusted_mode.crtc_clock = pipe_config->port_clock;
> > +}
> > +
> > static void
> > intel_ddi_calculate_wrpll(int clock /* in Hz */,
> > unsigned *r2_out, unsigned *n2_out, unsigned *p_out)
> > @@ -1504,6 +1594,8 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
> > pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
> > dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
> > }
> > +
> > + intel_ddi_clock_get(encoder, pipe_config);
> > }
> >
> > static void intel_ddi_destroy(struct drm_encoder *encoder)
> > --
> > 1.8.3.2
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Ville Syrjälä
> Intel OTC
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2014-01-22 9:46 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2014-01-20 22:18 [PATCH 1/2] drm/i915: clock readout support for DDI v2 Jesse Barnes
2014-01-20 22:18 ` [PATCH 2/2] drm/i915: always check clocks when comparing pipe configs Jesse Barnes
2014-01-21 11:36 ` [PATCH 1/2] drm/i915: clock readout support for DDI v2 Ville Syrjälä
2014-01-21 20:38 ` Jesse Barnes
2014-01-21 20:42 ` [PATCH] drm/i915: clock readout support for DDI v3 Jesse Barnes
2014-01-22 8:56 ` Ville Syrjälä
2014-01-22 9:46 ` Daniel Vetter
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