From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH v4 1/3] drm/i915: Disable/Enable PM Intrrupts based on the current freq. Date: Tue, 21 Jan 2014 16:34:43 +0200 Message-ID: <20140121143443.GD9454@intel.com> References: <1390223426-27627-1-git-send-email-deepak.s@intel.com> <1390223426-27627-2-git-send-email-deepak.s@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTP id E9580FB4B3 for ; Tue, 21 Jan 2014 06:38:28 -0800 (PST) Content-Disposition: inline In-Reply-To: <1390223426-27627-2-git-send-email-deepak.s@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org To: deepak.s@intel.com Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Mon, Jan 20, 2014 at 06:40:24PM +0530, deepak.s@intel.com wrote: > From: Deepak S > = > When current delay is already at max delay, Let's disable the PM UP > THRESHOLD INTRRUPTS, so that we will not get further interrupts until > current delay is less than max delay, Also request for the PM DOWN > THRESHOLD INTRRUPTS to indicate the decrease in clock freq. and > viceversa for PM DOWN THRESHOLD INTRRUPTS. > = > v2: Use bool variables (Daniel) > = > v3: Fix Interrupt masking bit (Deepak) > = > v4: Use existing symbolic constants in i915_reg.h (Daniel) > = > Signed-off-by: Deepak S > --- > drivers/gpu/drm/i915/i915_drv.h | 3 +++ > drivers/gpu/drm/i915/i915_irq.c | 31 +++++++++++++++++++++++++++++-- > drivers/gpu/drm/i915/intel_pm.c | 3 +++ > 3 files changed, 35 insertions(+), 2 deletions(-) > = > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_= drv.h > index f888fea..e89b9f4 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -943,6 +943,9 @@ struct intel_gen6_power_mgmt { > u8 rp0_delay; > u8 hw_max; > = > + bool rp_up_masked; > + bool rp_down_masked; > + > int last_adj; > enum { LOW_POWER, BETWEEN, HIGH_POWER } power; > = > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_= irq.c > index 160d65d..d0d87ed 100644 > --- a/drivers/gpu/drm/i915/i915_irq.c > +++ b/drivers/gpu/drm/i915/i915_irq.c > @@ -993,7 +993,20 @@ static void gen6_pm_rps_work(struct work_struct *wor= k) > adj *=3D 2; > else > adj =3D 1; > - new_delay =3D dev_priv->rps.cur_delay + adj; > + > + if (dev_priv->rps.cur_delay >=3D dev_priv->rps.max_delay) { > + I915_WRITE(GEN6_PMINTRMSK, > + I915_READ(GEN6_PMINTRMSK) | GEN6_PM_RP_UP_THRESHOLD); > + dev_priv->rps.rp_up_masked =3D true; > + new_delay =3D dev_priv->rps.cur_delay; > + } else > + new_delay =3D dev_priv->rps.cur_delay + adj; > + > + if (dev_priv->rps.rp_down_masked) { > + I915_WRITE(GEN6_PMINTRMSK, > + I915_READ(GEN6_PMINTRMSK) & ~GEN6_PM_RP_DOWN_THRESHOLD); > + dev_priv->rps.rp_down_masked =3D false; > + } At this point we've not yet computed the final new_delay. It would seem better to me to put all this code to place where we have the final new_delay. Also I wonder if we should also mask the DOWN_TIMEOUT interrupt? > = > /* > * For better performance, jump directly > @@ -1012,7 +1025,21 @@ static void gen6_pm_rps_work(struct work_struct *w= ork) > adj *=3D 2; > else > adj =3D -1; > - new_delay =3D dev_priv->rps.cur_delay + adj; > + > + if (dev_priv->rps.cur_delay <=3D dev_priv->rps.min_delay) { > + I915_WRITE(GEN6_PMINTRMSK, > + I915_READ(GEN6_PMINTRMSK) | GEN6_PM_RP_DOWN_THRESHOLD); > + dev_priv->rps.rp_down_masked =3D true; > + new_delay =3D dev_priv->rps.cur_delay; > + } else > + new_delay =3D dev_priv->rps.cur_delay + adj; > + > + if (dev_priv->rps.rp_up_masked) { > + I915_WRITE(GEN6_PMINTRMSK, > + I915_READ(GEN6_PMINTRMSK) & ~GEN6_PM_RP_UP_THRESHOLD); > + dev_priv->rps.rp_up_masked =3D false; > + } Same comments apply. > + > } else { /* unknown event */ > new_delay =3D dev_priv->rps.cur_delay; > } > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel= _pm.c > index b9b4fe4..d00a2cf 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -3613,6 +3613,9 @@ static void valleyview_enable_rps(struct drm_device= *dev) > vlv_gpu_freq(dev_priv, dev_priv->rps.rpe_delay), > dev_priv->rps.rpe_delay); > = > + dev_priv->rps.rp_up_masked =3D false; > + dev_priv->rps.rp_down_masked =3D false; > + > valleyview_set_rps(dev_priv->dev, dev_priv->rps.rpe_delay); > = > gen6_enable_rps_interrupts(dev); > -- = > 1.8.4.2 > = > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- = Ville Syrj=E4l=E4 Intel OTC