From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH 1/6] drm/i915/vlv: Added a rendering specific Hw WA 'WaTlbInvalidateStoreDataBefore' Date: Wed, 22 Jan 2014 12:51:01 +0200 Message-ID: <20140122105101.GJ9454@intel.com> References: <1390362310-15963-1-git-send-email-akash.goel@intel.com> <1390362310-15963-2-git-send-email-akash.goel@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTP id C2886FA80A for ; Wed, 22 Jan 2014 02:53:33 -0800 (PST) Content-Disposition: inline In-Reply-To: <1390362310-15963-2-git-send-email-akash.goel@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org To: akash.goel@intel.com Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Wed, Jan 22, 2014 at 09:15:05AM +0530, akash.goel@intel.com wrote: > From: Akash Goel > = > Added a new rendering specific Workaround 'WaTlbInvalidateStoreDataBefore= '. > In this WA, before pipecontrol with TLB invalidate set, need to add 2 MI > Store data commands. > = > Signed-off-by: Akash Goel > --- > drivers/gpu/drm/i915/intel_ringbuffer.c | 22 ++++++++++++++++++++++ > 1 file changed, 22 insertions(+) > = > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i9= 15/intel_ringbuffer.c > index 442c9a6..133d273 100644 > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c > @@ -2177,6 +2177,28 @@ intel_ring_invalidate_all_caches(struct intel_ring= _buffer *ring) > uint32_t flush_domains; > int ret; > = > + if (IS_VALLEYVIEW(ring->dev)) { > + /* > + * WaTlbInvalidateStoreDataBefore > + * Before pipecontrol with TLB invalidate set, need 2 store > + * data commands (such as MI_STORE_DATA_IMM or MI_STORE_DATA_INDEX) > + * Without this, hardware cannot guarantee the command after the > + * PIPE_CONTROL with TLB inv will not use the old TLB values. > + */ > + int i; > + ret =3D intel_ring_begin(ring, 4 * 2); > + if (ret) > + return ret; > + for (i =3D 0; i < 2; i++) { > + intel_ring_emit(ring, MI_STORE_DWORD_INDEX); > + intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_INDEX << > + MI_STORE_DWORD_INDEX_SHIFT); > + intel_ring_emit(ring, 0); > + intel_ring_emit(ring, MI_NOOP); > + } > + intel_ring_advance(ring); > + } This workaround is listed for everything SNB+, so it would seem we should just check for gen>=3D6. Also I think it should be placed inside the ring .flush() functions since we call those w/ invalidate_domains!=3D0 from other places as well. > + > flush_domains =3D 0; > if (ring->gpu_caches_dirty) > flush_domains =3D I915_GEM_GPU_DOMAINS; > -- = > 1.8.5.2 > = > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- = Ville Syrj=E4l=E4 Intel OTC