From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH 2/6] drm/i915/vlv: Added a rendering specific Hw WA 'WaReadAfterWriteHazard' Date: Wed, 22 Jan 2014 12:54:51 +0200 Message-ID: <20140122105451.GK9454@intel.com> References: <1390362310-15963-1-git-send-email-akash.goel@intel.com> <1390362310-15963-3-git-send-email-akash.goel@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTP id 14391FAAEE for ; Wed, 22 Jan 2014 02:54:55 -0800 (PST) Content-Disposition: inline In-Reply-To: <1390362310-15963-3-git-send-email-akash.goel@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org To: akash.goel@intel.com Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Wed, Jan 22, 2014 at 09:15:06AM +0530, akash.goel@intel.com wrote: > From: Akash Goel > = > Added a new rendering specific Workaround 'WaReadAfterWriteHazard'. > In this WA, need to add 12 MI Store Dword commands to ensure proper > flush of h/w pipeline. > = > Signed-off-by: Akash Goel > --- > drivers/gpu/drm/i915/intel_ringbuffer.c | 25 +++++++++++++++++++++++++ > 1 file changed, 25 insertions(+) > = > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i9= 15/intel_ringbuffer.c > index 133d273..e8ec536 100644 > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c > @@ -2167,6 +2167,31 @@ intel_ring_flush_all_caches(struct intel_ring_buff= er *ring) > = > trace_i915_gem_ring_flush(ring, 0, I915_GEM_GPU_DOMAINS); > = > + if (IS_VALLEYVIEW(ring->dev)) { > + /* > + * WaReadAfterWriteHazard > + * Send a number of Store Data commands here to finish > + * flushing hardware pipeline.This is needed in the case > + * where the next workload tries reading from the same > + * surface that this batch writes to. Without these StoreDWs, > + * not all of the data will actually be flushd to the surface > + * by the time the next batch starts reading it, possibly > + * causing a small amount of corruption. > + */ > + int i; > + ret =3D intel_ring_begin(ring, 4 * 12); BSpec says 8 is enough. Is Bspec incorrect. Also this workaround is also listed for everything SNB+. > + if (ret) > + return ret; > + for (i =3D 0; i < 12; i++) { > + intel_ring_emit(ring, MI_STORE_DWORD_INDEX); > + intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_INDEX << > + MI_STORE_DWORD_INDEX_SHIFT); > + intel_ring_emit(ring, 0); > + intel_ring_emit(ring, MI_NOOP); > + } > + intel_ring_advance(ring); > + } > + > ring->gpu_caches_dirty =3D false; > return 0; > } > -- = > 1.8.5.2 > = > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- = Ville Syrj=E4l=E4 Intel OTC