From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH 3/6] drm/i915/vlv: Modified the programming of 2 regs in Ring initialisation Date: Wed, 22 Jan 2014 13:01:04 +0200 Message-ID: <20140122110103.GL9454@intel.com> References: <1390362310-15963-1-git-send-email-akash.goel@intel.com> <1390362310-15963-4-git-send-email-akash.goel@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTP id ADF521059D0 for ; Wed, 22 Jan 2014 03:01:31 -0800 (PST) Content-Disposition: inline In-Reply-To: <1390362310-15963-4-git-send-email-akash.goel@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org To: akash.goel@intel.com Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Wed, Jan 22, 2014 at 09:15:07AM +0530, akash.goel@intel.com wrote: > From: Akash Goel > = > Modified programming of following 2 regs in Render ring initialisation fn. > 1. GFX_MODE_GEN7 (Enabling TLB invalidate) > 2. MI_MODE (Enabling MI Flush) > = > Signed-off-by: Akash Goel > --- > drivers/gpu/drm/i915/intel_ringbuffer.c | 19 ++++++++++++++----- > 1 file changed, 14 insertions(+), 5 deletions(-) > = > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i9= 15/intel_ringbuffer.c > index e8ec536..8b99df2 100644 > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c > @@ -563,7 +563,9 @@ static int init_render_ring(struct intel_ring_buffer = *ring) > int ret =3D init_ring_common(ring); > = > if (INTEL_INFO(dev)->gen > 3) > - I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH)); > + if (!IS_VALLEYVIEW(dev)) > + I915_WRITE(MI_MODE, > + _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH)); BSpec says this should be enabled for everything before IVB. So based on that the condition should just be 'if (gen > 3 && gen < 7)' > = > /* We need to disable the AsyncFlip performance optimisations in order > * to use MI_WAIT_FOR_EVENT within the CS. It should already be > @@ -579,10 +581,17 @@ static int init_render_ring(struct intel_ring_buffe= r *ring) > I915_WRITE(GFX_MODE, > _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_ALWAYS)); > = > - if (IS_GEN7(dev)) > - I915_WRITE(GFX_MODE_GEN7, > - _MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) | > - _MASKED_BIT_ENABLE(GFX_REPLAY_MODE)); > + if (IS_GEN7(dev)) { > + if (IS_VALLEYVIEW(dev)) { > + I915_WRITE(GFX_MODE_GEN7, > + _MASKED_BIT_ENABLE(GFX_REPLAY_MODE)); > + I915_WRITE(MI_MODE, I915_READ(MI_MODE) | > + _MASKED_BIT_ENABLE(MI_FLUSH_ENABLE)); Why do we need to enable MI_FLUSH, and why only for VLV? > + } else > + I915_WRITE(GFX_MODE_GEN7, > + _MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) | > + _MASKED_BIT_ENABLE(GFX_REPLAY_MODE)); > + } According to BSpec the GFX_TLB_INVALIDATE_ALWAYS bit only exists on SNB. So it would we should just drop it here. > = > if (INTEL_INFO(dev)->gen >=3D 5) { > ret =3D init_pipe_control(ring); > -- = > 1.8.5.2 > = > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- = Ville Syrj=E4l=E4 Intel OTC