From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH 5/6] drm/i915/vlv: Removed 3 rendering specific Hw WA from clock gating fn Date: Wed, 22 Jan 2014 13:11:43 +0200 Message-ID: <20140122111143.GN9454@intel.com> References: <1390362310-15963-1-git-send-email-akash.goel@intel.com> <1390362310-15963-6-git-send-email-akash.goel@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTP id 89525FB8BD for ; Wed, 22 Jan 2014 03:11:46 -0800 (PST) Content-Disposition: inline In-Reply-To: <1390362310-15963-6-git-send-email-akash.goel@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: akash.goel@intel.com Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Wed, Jan 22, 2014 at 09:15:09AM +0530, akash.goel@intel.com wrote: > From: Akash Goel > = > Removed 3 workarounds as not needed for VLV+(B0 onwards) > 1. WaDisableRHWOOptimizationForRenderHang > 2. WaDisableL3CacheAging > 3. WaDisableDopClockGating Again multiple patches. And I think my earlier series already touched on some of these. > = > Signed-off-by: Akash Goel > --- > drivers/gpu/drm/i915/intel_pm.c | 10 ---------- > 1 file changed, 10 deletions(-) > = > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel= _pm.c > index 4c36ff8..e4d220c 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -4947,12 +4947,6 @@ static void valleyview_init_clock_gating(struct dr= m_device *dev) > _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP | > GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE)); > = > - /* Apply the WaDisableRHWOOptimizationForRenderHang:vlv workaround. */ > - I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1, > - GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC); > - > - /* WaApplyL3ControlAndL3ChickenMode:vlv */ > - I915_WRITE(GEN7_L3CNTLREG1, I915_READ(GEN7_L3CNTLREG1) | GEN7_L3AGDIS); > I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE); > = > /* WaDisable_RenderCache_OperationalFlush > @@ -4965,10 +4959,6 @@ static void valleyview_init_clock_gating(struct dr= m_device *dev) > I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) & > ~L3SQ_URB_READ_CAM_MATCH_DISABLE); > = > - /* WaDisableDopClockGating:vlv */ > - I915_WRITE(GEN7_ROW_CHICKEN2, > - _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); > - > /* This is required by WaCatErrorRejectionIssue:vlv */ > I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, > I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | > -- = > 1.8.5.2 > = > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- = Ville Syrj=E4l=E4 Intel OTC