From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH 6/6] drm/i915/vlv: Added a rendering specific Hw WA 'WaSendDummy3dPrimitveAfterSetContext' Date: Wed, 22 Jan 2014 13:18:45 +0200 Message-ID: <20140122111845.GO9454@intel.com> References: <1390362310-15963-1-git-send-email-akash.goel@intel.com> <1390362310-15963-7-git-send-email-akash.goel@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTP id 2A6CD105966 for ; Wed, 22 Jan 2014 03:18:49 -0800 (PST) Content-Disposition: inline In-Reply-To: <1390362310-15963-7-git-send-email-akash.goel@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org To: akash.goel@intel.com Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Wed, Jan 22, 2014 at 09:15:10AM +0530, akash.goel@intel.com wrote: > From: Akash Goel > = > This workaround is needed on VLV for the HW context feature. > It is used after adding the mi_set_context command in ring buffer > for Hw context switch. As per the spec > "The software must send a pipe_control with a CS stall and a post sync > operation and then a dummy DRAW after every MI_SET_CONTEXT and after any > PIPELINE_SELECT that is enabling 3D mode". This is also listed for IVB. > = > Signed-off-by: Akash Goel > --- > drivers/gpu/drm/i915/i915_gem_context.c | 64 +++++++++++++++++++++++++++= ++++-- > drivers/gpu/drm/i915/i915_reg.h | 3 ++ > drivers/gpu/drm/i915/intel_ringbuffer.c | 9 +++++ > drivers/gpu/drm/i915/intel_ringbuffer.h | 1 + > 4 files changed, 75 insertions(+), 2 deletions(-) > = > diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i9= 15/i915_gem_context.c > index ebe0f67..62a5362 100644 > --- a/drivers/gpu/drm/i915/i915_gem_context.c > +++ b/drivers/gpu/drm/i915/i915_gem_context.c > @@ -532,6 +532,58 @@ i915_gem_context_get(struct drm_i915_file_private *f= ile_priv, u32 id) > return (struct i915_hw_context *)idr_find(&file_priv->context_idr, id); > } > = > +static inline void > +mi_set_context_dummy3d_prim_wa(struct intel_ring_buffer *ring) > +{ > + u32 scratch_addr; > + u32 flags =3D 0; > + > + /* > + * Check if we have the scratch page allocated needed > + * for the Pipe Control command, otherwise don't apply > + * the dummmy 3d primitive workaround & add NOOPs instead > + */ > + if (get_pipe_control_scratch_addr(ring)) { > + /* Actual scratch location is at 128 bytes offset */ > + scratch_addr =3D get_pipe_control_scratch_addr(ring) + 128; > + > + /* > + * WaSendDummy3dPrimitveAfterSetContext > + * Software must send a pipe_control with a CS stall > + * and a post sync operation and then a dummy DRAW after > + * every MI_SET_CONTEXT and after any PIPELINE_SELECT that > + * is enabling 3D mode. A dummy draw is a 3DPRIMITIVE command > + * with Indirect Parameter Enable set to 0, UAV Coherency > + * Required set to 0, Predicate Enable set to 0, > + * End Offset Enable set to 0, and Vertex Count Per Instance > + * set to 0, All other parameters are a don't care. > + */ > + > + /* > + * Add a pipe control with CS Stall and postsync op > + * before dummy 3D_PRIMITIVE > + */ > + flags |=3D PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL; > + intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); > + intel_ring_emit(ring, flags); > + intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); > + intel_ring_emit(ring, 0); > + > + /* Add a dummy 3D_PRIMITVE */ > + intel_ring_emit(ring, GFX_OP_3DPRIMITIVE()); > + intel_ring_emit(ring, 4); /* PrimTopoType*/ > + intel_ring_emit(ring, 0); /* VertexCountPerInstance */ > + intel_ring_emit(ring, 0); /* StartVertexLocation */ > + intel_ring_emit(ring, 0); /* InstanceCount */ > + intel_ring_emit(ring, 0); /* StartInstanceLocation */ > + intel_ring_emit(ring, 0); /* BaseVertexLocation */ > + } else { > + int i; > + for (i =3D 0; i < 11; i++) > + intel_ring_emit(ring, MI_NOOP); > + } > +} > + > static inline int > mi_set_context(struct intel_ring_buffer *ring, > struct i915_hw_context *new_context, > @@ -550,7 +602,10 @@ mi_set_context(struct intel_ring_buffer *ring, > return ret; > } > = > - ret =3D intel_ring_begin(ring, 6); > + if (IS_VALLEYVIEW(ring->dev)) > + ret =3D intel_ring_begin(ring, 6+4+8); > + else > + ret =3D intel_ring_begin(ring, 6); > if (ret) > return ret; > = > @@ -571,7 +626,12 @@ mi_set_context(struct intel_ring_buffer *ring, > intel_ring_emit(ring, MI_NOOP); > = > if (IS_GEN7(ring->dev)) > - intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_ENABLE); > + if (IS_VALLEYVIEW(ring->dev)) { > + mi_set_context_dummy3d_prim_wa(ring); > + intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_ENABLE); > + intel_ring_emit(ring, MI_NOOP); > + } else > + intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_ENABLE); > else > intel_ring_emit(ring, MI_NOOP); > = > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_= reg.h > index d829754..649106d 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -335,6 +335,9 @@ > #define PIPE_CONTROL_DEPTH_CACHE_FLUSH (1<<0) > #define PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */ > = > +#define GFX_OP_3DPRIMITIVE() \ > + ((0x3<<29)|(0x3<<27)|(0x3<<24)| \ > + (0x0<<16)|(0x0<<10)|(0x0<<8)|(7-2)) > = > /* > * Reset registers > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i9= 15/intel_ringbuffer.c > index 8b99df2..a93b631 100644 > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c > @@ -556,6 +556,15 @@ err: > return ret; > } > = > +u32 > +get_pipe_control_scratch_addr(struct intel_ring_buffer *ring) > +{ > + if (ring->scratch.obj =3D=3D NULL) > + return 0; > + > + return ring->scratch.gtt_offset; > +} > + > static int init_render_ring(struct intel_ring_buffer *ring) > { > struct drm_device *dev =3D ring->dev; > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i9= 15/intel_ringbuffer.h > index 71a73f4..2ae6029 100644 > --- a/drivers/gpu/drm/i915/intel_ringbuffer.h > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h > @@ -257,6 +257,7 @@ int intel_init_vebox_ring_buffer(struct drm_device *d= ev); > = > u32 intel_ring_get_active_head(struct intel_ring_buffer *ring); > void intel_ring_setup_status_page(struct intel_ring_buffer *ring); > +u32 get_pipe_control_scratch_addr(struct intel_ring_buffer *ring); > = > static inline u32 intel_ring_get_tail(struct intel_ring_buffer *ring) > { > -- = > 1.8.5.2 > = > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- = Ville Syrj=E4l=E4 Intel OTC