From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH] drm/i915: Set primary plane enable at dpcntrl. Date: Fri, 24 Jan 2014 16:58:05 +0200 Message-ID: <20140124145805.GI9454@intel.com> References: <1390501010-4641-1-git-send-email-rodrigo.vivi@gmail.com> <1390504759-6078-1-git-send-email-rodrigo.vivi@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTP id C7B4AF9F39 for ; Fri, 24 Jan 2014 06:58:09 -0800 (PST) Content-Disposition: inline In-Reply-To: <1390504759-6078-1-git-send-email-rodrigo.vivi@gmail.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org To: Rodrigo Vivi Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Thu, Jan 23, 2014 at 05:19:19PM -0200, Rodrigo Vivi wrote: > This patch allows system to safely recover after kms_psr_sink_crc check > or any other similar case that might fail when PSR is enabled. > = > Ville made and sent me this patch after noticing that primary plane enabl= ed > bit was set during test case and unset after failure. What was causing a = hard > and non-recoverable blank screen. > = > After the failure when alternating from fbcon to x section it was possibl= e to > see and move mouse cursor, but nothing else. Everything else was fully bl= ack. > A for dpms off/on also haleped to get screen back. But this patch seeting > primary plane enabled bit propertly seemed more clean. > = > v2: Fix identation issue. > = > Cc: Ville Syrj=E4l=E4 > Signed-off-by: Rodrigo Vivi > --- > drivers/gpu/drm/i915/intel_display.c | 11 +++++++++++ > 1 file changed, 11 insertions(+) > = > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/= intel_display.c > index dde98020..ed5ffce 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -2095,6 +2095,9 @@ static int i9xx_update_plane(struct drm_crtc *crtc,= struct drm_framebuffer *fb, > if (IS_G4X(dev)) > dspcntr |=3D DISPPLANE_TRICKLE_FEED_DISABLE; > = > + if (intel_crtc->primary_enabled) > + dspcntr |=3D DISPLAY_PLANE_ENABLE; > + > I915_WRITE(reg, dspcntr); > = > linear_offset =3D y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); > @@ -2192,6 +2195,9 @@ static int ironlake_update_plane(struct drm_crtc *c= rtc, > else > dspcntr |=3D DISPPLANE_TRICKLE_FEED_DISABLE; > = > + if (intel_crtc->primary_enabled) > + dspcntr |=3D DISPLAY_PLANE_ENABLE; > + > I915_WRITE(reg, dspcntr); > = > linear_offset =3D y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); > @@ -8586,6 +8592,11 @@ static int intel_gen7_queue_flip(struct drm_device= *dev, > intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspad= dr_offset); > intel_ring_emit(ring, (MI_NOOP)); > = > + if (IS_VALLEYVIEW(dev) && intel_crtc->primary_enabled) > + I915_WRITE(DSPCNTR(intel_crtc->plane), > + I915_READ(DSPCNTR(intel_crtc->plane)) > + | DISPLAY_PLANE_ENABLE); We should add some kind of big comment that this ugly hack is here for PSR. I assume we're going to remove it eventually once someone figures out why the port/pipe/PLL aren't shutting down during PSR. To wake the hardware back from that state takes a lot more than just flipping a plane enable bit. > + > intel_mark_page_flip_active(intel_crtc); > __intel_ring_advance(ring); > return 0; > -- = > 1.8.1.2 -- = Ville Syrj=E4l=E4 Intel OTC