From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH 08/28] drm/i915: Fix IVB GT2 WaDisableDopClockGating and WaDisablePSDDualDispatchEnable Date: Fri, 24 Jan 2014 19:58:45 +0200 Message-ID: <20140124175845.GL9454@intel.com> References: <1390419184-4450-1-git-send-email-ville.syrjala@linux.intel.com> <1390419184-4450-9-git-send-email-ville.syrjala@linux.intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTP id 0AB55FA7DD for ; Fri, 24 Jan 2014 09:58:48 -0800 (PST) Content-Disposition: inline In-Reply-To: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org To: Rodrigo Vivi Cc: intel-gfx List-Id: intel-gfx@lists.freedesktop.org On Fri, Jan 24, 2014 at 03:32:08PM -0200, Rodrigo Vivi wrote: > Your patch itself makes sense, but the registers values there are at i915= _reg.h > differs from what I see at BSpec: > = > #define GEN7_ROW_CHICKEN2 0xe4f4 > #define GEN7_ROW_CHICKEN2_GT2 0xf4f4 > = > against > Address: 0E4F0h > Valid Projects: [DevIVB, EXCLUDE(DevIVB:GT2)] > Address: 0F4F0h > Valid Projects: [DevIVB:GT2] ROW_CHICKEN vs. ROW_CHICKEN2 > = > Also, I couldn't see the wa description at wa_database... > description was empty for me.. Which one? WaDisableDopClockGating? It's not in the list for IVB, so in order to see it you need to pick another platform which includes this w/a. > = > On Wed, Jan 22, 2014 at 5:32 PM, wrote: > > From: Ville Syrj=E4l=E4 > > > > IVB GT2 has two registers for these things, and both must be written. > > > > To add a bit more confusion both Bspec and the W/A database state that > > WaDisablePSDDualDispatchEnable is only needed for IVB GT1, but the W/A > > database also says to write even the second GT2 only register. So I > > don't really know what the right thing here is. > > > > Signed-off-by: Ville Syrj=E4l=E4 > > --- > > drivers/gpu/drm/i915/intel_pm.c | 13 ++++++++++--- > > 1 file changed, 10 insertions(+), 3 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/int= el_pm.c > > index 6a1d98a..b268a55 100644 > > --- a/drivers/gpu/drm/i915/intel_pm.c > > +++ b/drivers/gpu/drm/i915/intel_pm.c > > @@ -4828,9 +4828,13 @@ static void ivybridge_init_clock_gating(struct d= rm_device *dev) > > if (IS_IVB_GT1(dev)) > > I915_WRITE(GEN7_HALF_SLICE_CHICKEN1, > > _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISP= ATCH_ENABLE)); > > - else > > + else { > > + /* must write both registers */ > > + I915_WRITE(GEN7_HALF_SLICE_CHICKEN1, > > + _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISP= ATCH_ENABLE)); > > I915_WRITE(GEN7_HALF_SLICE_CHICKEN1_GT2, > > _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISP= ATCH_ENABLE)); > > + } > > > > /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaro= und. */ > > I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1, > > @@ -4846,10 +4850,13 @@ static void ivybridge_init_clock_gating(struct = drm_device *dev) > > if (IS_IVB_GT1(dev)) > > I915_WRITE(GEN7_ROW_CHICKEN2, > > _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)= ); > > - else > > + else { > > + /* must write both registers */ > > + I915_WRITE(GEN7_ROW_CHICKEN2, > > + _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)= ); > > I915_WRITE(GEN7_ROW_CHICKEN2_GT2, > > _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)= ); > > - > > + } > > > > /* WaForceL3Serialization:ivb */ > > I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) & > > -- > > 1.8.3.2 > > > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > http://lists.freedesktop.org/mailman/listinfo/intel-gfx > = > = > = > -- = > Rodrigo Vivi > Blog: http://blog.vivi.eng.br -- = Ville Syrj=E4l=E4 Intel OTC