From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH 05/10] drm/i915: Use 1/2 compression ratio limit for 16bpp on FBC2 Date: Mon, 27 Jan 2014 11:41:19 +0200 Message-ID: <20140127094119.GO9454@intel.com> References: <1390488557-16003-1-git-send-email-ville.syrjala@linux.intel.com> <1390488557-16003-6-git-send-email-ville.syrjala@linux.intel.com> <20140125195734.GH9772@phenom.ffwll.local> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTP id 69EC2FAA7D for ; Mon, 27 Jan 2014 01:41:47 -0800 (PST) Content-Disposition: inline In-Reply-To: <20140125195734.GH9772@phenom.ffwll.local> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Daniel Vetter Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Sat, Jan 25, 2014 at 08:57:34PM +0100, Daniel Vetter wrote: > On Thu, Jan 23, 2014 at 04:49:12PM +0200, ville.syrjala@linux.intel.com w= rote: > > From: Ville Syrj=E4l=E4 > > = > > Signed-off-by: Ville Syrj=E4l=E4 > = > Hm, running the fbc tests with a 16bpp fb would be neat ... Indeed. I'll put it on the list. > -Daniel > = > > --- > > drivers/gpu/drm/i915/intel_pm.c | 24 +++++++++++++++++++----- > > 1 file changed, 19 insertions(+), 5 deletions(-) > > = > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/int= el_pm.c > > index c6e047e..a7af5b4 100644 > > --- a/drivers/gpu/drm/i915/intel_pm.c > > +++ b/drivers/gpu/drm/i915/intel_pm.c > > @@ -155,7 +155,11 @@ static void g4x_enable_fbc(struct drm_crtc *crtc) > > struct intel_crtc *intel_crtc =3D to_intel_crtc(crtc); > > u32 dpfc_ctl; > > = > > - dpfc_ctl =3D DPFC_CTL_PLANE(intel_crtc->plane) | DPFC_SR_EN | DPFC_CT= L_LIMIT_1X; > > + dpfc_ctl =3D DPFC_CTL_PLANE(intel_crtc->plane) | DPFC_SR_EN; > > + if (drm_format_plane_cpp(fb->pixel_format, 0) =3D=3D 2) > > + dpfc_ctl |=3D DPFC_CTL_LIMIT_2X; > > + else > > + dpfc_ctl |=3D DPFC_CTL_LIMIT_1X; > > dpfc_ctl |=3D DPFC_CTL_FENCE_EN | obj->fence_reg; > > = > > I915_WRITE(DPFC_FENCE_YOFF, crtc->y); > > @@ -225,7 +229,11 @@ static void ironlake_enable_fbc(struct drm_crtc *c= rtc) > > = > > dpfc_ctl =3D I915_READ(ILK_DPFC_CONTROL); > > dpfc_ctl &=3D DPFC_RESERVED; > > - dpfc_ctl |=3D DPFC_CTL_PLANE(intel_crtc->plane) | DPFC_CTL_LIMIT_1X; > > + dpfc_ctl |=3D DPFC_CTL_PLANE(intel_crtc->plane); > > + if (drm_format_plane_cpp(fb->pixel_format, 0) =3D=3D 2) > > + dpfc_ctl |=3D DPFC_CTL_LIMIT_2X; > > + else > > + dpfc_ctl |=3D DPFC_CTL_LIMIT_1X; > > dpfc_ctl |=3D DPFC_CTL_FENCE_EN; > > if (IS_GEN5(dev)) > > dpfc_ctl |=3D obj->fence_reg; > > @@ -275,10 +283,16 @@ static void gen7_enable_fbc(struct drm_crtc *crtc) > > struct intel_framebuffer *intel_fb =3D to_intel_framebuffer(fb); > > struct drm_i915_gem_object *obj =3D intel_fb->obj; > > struct intel_crtc *intel_crtc =3D to_intel_crtc(crtc); > > + u32 dpfc_ctl; > > = > > - I915_WRITE(ILK_DPFC_CONTROL, DPFC_CTL_EN | DPFC_CTL_LIMIT_1X | > > - IVB_DPFC_CTL_FENCE_EN | > > - IVB_DPFC_CTL_PLANE(intel_crtc->plane)); > > + dpfc_ctl =3D IVB_DPFC_CTL_PLANE(intel_crtc->plane); > > + if (drm_format_plane_cpp(fb->pixel_format, 0) =3D=3D 2) > > + dpfc_ctl |=3D DPFC_CTL_LIMIT_2X; > > + else > > + dpfc_ctl |=3D DPFC_CTL_LIMIT_1X; > > + dpfc_ctl |=3D IVB_DPFC_CTL_FENCE_EN; > > + > > + I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); > > = > > if (IS_IVYBRIDGE(dev)) { > > /* WaFbcAsynchFlipDisableFbcQueue:ivb */ > > -- = > > 1.8.3.2 > > = > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > http://lists.freedesktop.org/mailman/listinfo/intel-gfx > = > -- = > Daniel Vetter > Software Engineer, Intel Corporation > +41 (0) 79 365 57 48 - http://blog.ffwll.ch -- = Ville Syrj=E4l=E4 Intel OTC