[PATCH 00/28] drm/i915: Lots of workaround changes (resurrected)

[PATCH 00/28] drm/i915: Lots of workaround changes (resurrected)

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Here's a resurrected version of my workaround cleanup series from last
summer. I dropped a few patches I deemed incorrect and rebased the lot.

I also added the VLV clock gating revert on top. I had that patch sitting
in a branch but apparently never sent it out.

I've today tested these briefly on an IVB, HSW and VLV. And IIRC I was
running them also for a while last summer on IVB and VLV.

Ville Syrjälä (28):
  drm/i915: We implement WaDisableL3Bank2xClockGate:vlv
  drm/i915: We implement
    WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw
  drm/i915: WaPsdDispatchEnable seems to be another name for
    WaDisablePSDDualDispatchEnable
  drm/i915: We implement WaDisableL3CacheAging:vlv
  drm/i915: We implement WaDisableDopClockGating:ivb
  drm/i915: We implement WaDisableRCCUnitClockGating:snb
  drm/i915: We implement WaMiSetContext_Hang
  drm/i915: Fix IVB GT2 WaDisableDopClockGating and
    WaDisablePSDDualDispatchEnable
  drm/i915: Drop WaDisablePSDDualDispatchEnable:ivb for IVB GT2
  drm/i915: Implement WaIncreaseL3CreditsForVLVB0:vlv
  drm/i915: WaDisableVDSUnitClockGating isn't applicable to SNB
  drm/i915: WaDisableRCCUnitClockGating isn't applicable to IVB
  drm/i915: WaDisableRCCUnitClockGating isn't applicaple to VLV
  drm/i915: WaDisableRHWOOptimizationForRenderHang isn't applicable to
    HSW
  drm/i915: WaDisableRHWOOptimizationForRenderHang isn't applicable to
    VLV
  drm/i915: WaApplyL3ControlAndL3ChickenMode isn't applicable for VLV
  drm/i915: Drop bogus comment about RCPB unit clock gating on IVB
  drm/i915: Drop WaDisableRCZUnitClockGating:hsw
  drm/i915: Drop WaApplyL3ControlAndL3ChickenMode:hsw
  drm/i915: Drop WaDisableRCPBUnitClockGating:vlv
  drm/i915: Drop WaDisableVDSUtnitClockGating:vlv
  drm/i915: Drop WaDisableTDLUnitClockGating:vlv
  drm/i915: gen7_setup_fixed_func_scheduler() actually implements
    WaVSThreadDispatchOverride
  drm/i915: Don't apply WaVSThreadDispatchOverride on HSW
  drm/i915: VLV wants WaVSThreadDispatchOverride too
  drm/i915: WaDisableDopClockGating isn't applicable to IVB
  drm/i915: Clarify WaDisable4x2SubspanOptimization situation for VLV
  Revert "drm/i915: set conservative clock gating values on VLV v2"

 drivers/gpu/drm/i915/i915_gem_context.c |   5 +-
 drivers/gpu/drm/i915/i915_reg.h         |   3 +
 drivers/gpu/drm/i915/intel_display.c    |   1 +
 drivers/gpu/drm/i915/intel_pm.c         | 109 +++++++++-----------------------
 4 files changed, 38 insertions(+), 80 deletions(-)

-- 
1.8.3.2

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[PATCH 01/28] drm/i915: We implement WaDisableL3Bank2xClockGate:vlv

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index b9b4fe4..d18e43b 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4978,6 +4978,7 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
 		   GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
 		   GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
 
+	/* WaDisableL3Bank2xClockGate:vlv */
 	I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
 
 	I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
-- 
1.8.3.2

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Re: [PATCH 01/28] drm/i915: We implement WaDisableL3Bank2xClockGate:vlv

[Rodrigo Vivi]

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>

On Wed, Jan 22, 2014 at 5:32 PM,  <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index b9b4fe4..d18e43b 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4978,6 +4978,7 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
>                    GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
>                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
>
> +       /* WaDisableL3Bank2xClockGate:vlv */
>         I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
>
>         I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
> --
> 1.8.3.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br

[PATCH 02/28] drm/i915: We implement WaEnableVGAAccessThroughIOPort:ctg, elk, ilk, snb, ivb, vlv, hsw

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index ec96002..9006a87 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -10982,6 +10982,7 @@ static void i915_disable_vga(struct drm_device *dev)
 	u8 sr1;
 	u32 vga_reg = i915_vgacntrl_reg(dev);
 
+	/* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
 	vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
 	outb(SR01, VGA_SR_INDEX);
 	sr1 = inb(VGA_SR_DATA);
-- 
1.8.3.2

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Re: [PATCH 02/28] drm/i915: We implement WaEnableVGAAccessThroughIOPort:ctg, elk, ilk, snb, ivb, vlv, hsw

[Rodrigo Vivi]

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>

On Wed, Jan 22, 2014 at 5:32 PM,  <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index ec96002..9006a87 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -10982,6 +10982,7 @@ static void i915_disable_vga(struct drm_device *dev)
>         u8 sr1;
>         u32 vga_reg = i915_vgacntrl_reg(dev);
>
> +       /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
>         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
>         outb(SR01, VGA_SR_INDEX);
>         sr1 = inb(VGA_SR_DATA);
> --
> 1.8.3.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br

[PATCH 03/28] drm/i915: WaPsdDispatchEnable seems to be another name for WaDisablePSDDualDispatchEnable

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

The w/a database lists both WaPsdDispatchEnable and
WaDisablePSDDualDispatchEnable for VLV. They appear to be the same
thing, so list both names.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index d18e43b..6c0a10a 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4929,6 +4929,7 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
 		   CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
 		   CHICKEN3_DGMG_DONE_FIX_DISABLE);
 
+	/* WaPsdDispatchEnable:vlv */
 	/* WaDisablePSDDualDispatchEnable:vlv */
 	I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
 		   _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
-- 
1.8.3.2

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Re: [PATCH 03/28] drm/i915: WaPsdDispatchEnable seems to be another name for WaDisablePSDDualDispatchEnable

[Rodrigo Vivi]

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>

On Wed, Jan 22, 2014 at 5:32 PM,  <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> The w/a database lists both WaPsdDispatchEnable and
> WaDisablePSDDualDispatchEnable for VLV. They appear to be the same
> thing, so list both names.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index d18e43b..6c0a10a 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4929,6 +4929,7 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
>                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
>                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
>
> +       /* WaPsdDispatchEnable:vlv */
>         /* WaDisablePSDDualDispatchEnable:vlv */
>         I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
>                    _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
> --
> 1.8.3.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br

[PATCH 04/28] drm/i915: We implement WaDisableL3CacheAging:vlv

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 6c0a10a..0e724c9 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4939,8 +4939,9 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
 	I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
 		   GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
 
-	/* WaApplyL3ControlAndL3ChickenMode:vlv */
+	/* WaDisableL3CacheAging:vlv */
 	I915_WRITE(GEN7_L3CNTLREG1, I915_READ(GEN7_L3CNTLREG1) | GEN7_L3AGDIS);
+	/* WaApplyL3ControlAndL3ChickenMode:vlv */
 	I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE);
 
 	/* WaForceL3Serialization:vlv */
-- 
1.8.3.2

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Re: [PATCH 04/28] drm/i915: We implement WaDisableL3CacheAging:vlv

[Rodrigo Vivi]

On Wed, Jan 22, 2014 at 5:32 PM,  <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 6c0a10a..0e724c9 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4939,8 +4939,9 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
>         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
>                    GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
>
> -       /* WaApplyL3ControlAndL3ChickenMode:vlv */
> +       /* WaDisableL3CacheAging:vlv */

this is right.

>         I915_WRITE(GEN7_L3CNTLREG1, I915_READ(GEN7_L3CNTLREG1) | GEN7_L3AGDIS);
> +       /* WaApplyL3ControlAndL3ChickenMode:vlv */

On wa_database I only see this name with ivb...  nothing from vlv with
this wa name.

>         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE);
>
>         /* WaForceL3Serialization:vlv */
> --
> 1.8.3.2
>
> _______________________________________________
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-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br

Re: [PATCH 04/28] drm/i915: We implement WaDisableL3CacheAging:vlv

[Ville Syrjälä]

On Thu, Jan 23, 2014 at 06:25:26PM -0200, Rodrigo Vivi wrote:
> On Wed, Jan 22, 2014 at 5:32 PM,  <ville.syrjala@linux.intel.com> wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_pm.c | 3 ++-
> >  1 file changed, 2 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index 6c0a10a..0e724c9 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -4939,8 +4939,9 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
> >         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
> >                    GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
> >
> > -       /* WaApplyL3ControlAndL3ChickenMode:vlv */
> > +       /* WaDisableL3CacheAging:vlv */
> 
> this is right.
> 
> >         I915_WRITE(GEN7_L3CNTLREG1, I915_READ(GEN7_L3CNTLREG1) | GEN7_L3AGDIS);
> > +       /* WaApplyL3ControlAndL3ChickenMode:vlv */
> 
> On wa_database I only see this name with ivb...  nothing from vlv with
> this wa name.

Let me refer you to patch 16 in the series...

> 
> >         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE);
> >
> >         /* WaForceL3Serialization:vlv */
> > --
> > 1.8.3.2
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> 
> 
> -- 
> Rodrigo Vivi
> Blog: http://blog.vivi.eng.br

-- 
Ville Syrjälä
Intel OTC

Re: [PATCH 04/28] drm/i915: We implement WaDisableL3CacheAging:vlv

[Rodrigo Vivi]

On Thu, Jan 23, 2014 at 6:32 PM, Ville Syrjälä
<ville.syrjala@linux.intel.com> wrote:
> On Thu, Jan 23, 2014 at 06:25:26PM -0200, Rodrigo Vivi wrote:
>> On Wed, Jan 22, 2014 at 5:32 PM,  <ville.syrjala@linux.intel.com> wrote:
>> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> >
>> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> > ---
>> >  drivers/gpu/drm/i915/intel_pm.c | 3 ++-
>> >  1 file changed, 2 insertions(+), 1 deletion(-)
>> >
>> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
>> > index 6c0a10a..0e724c9 100644
>> > --- a/drivers/gpu/drm/i915/intel_pm.c
>> > +++ b/drivers/gpu/drm/i915/intel_pm.c
>> > @@ -4939,8 +4939,9 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
>> >         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
>> >                    GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
>> >
>> > -       /* WaApplyL3ControlAndL3ChickenMode:vlv */
>> > +       /* WaDisableL3CacheAging:vlv */
>>
>> this is right.
>>
>> >         I915_WRITE(GEN7_L3CNTLREG1, I915_READ(GEN7_L3CNTLREG1) | GEN7_L3AGDIS);
>> > +       /* WaApplyL3ControlAndL3ChickenMode:vlv */
>>
>> On wa_database I only see this name with ivb...  nothing from vlv with
>> this wa name.
>
> Let me refer you to patch 16 in the series...

Cool thanks.
Sorry for not check that... I'm going on blocks of 4 ;)

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
for this one as well.
>
>>
>> >         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE);
>> >
>> >         /* WaForceL3Serialization:vlv */
>> > --
>> > 1.8.3.2
>> >
>> > _______________________________________________
>> > Intel-gfx mailing list
>> > Intel-gfx@lists.freedesktop.org
>> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>>
>>
>>
>> --
>> Rodrigo Vivi
>> Blog: http://blog.vivi.eng.br
>
> --
> Ville Syrjälä
> Intel OTC



-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br

[PATCH 05/28] drm/i915: We implement WaDisableDopClockGating:ivb

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 0e724c9..bbaf8c7 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4840,6 +4840,8 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
 			GEN7_WA_FOR_GEN7_L3_CONTROL);
 	I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
 		   GEN7_WA_L3_CHICKEN_MODE);
+
+	/* WaDisableDopClockGating:ivb */
 	if (IS_IVB_GT1(dev))
 		I915_WRITE(GEN7_ROW_CHICKEN2,
 			   _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
-- 
1.8.3.2

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[PATCH 06/28] drm/i915: We implement WaDisableRCCUnitClockGating:snb

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index bbaf8c7..6a1d98a 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4606,6 +4606,7 @@ static void gen6_init_clock_gating(struct drm_device *dev)
 	 * but we didn't debug actual testcases to find it out.
 	 *
 	 * Also apply WaDisableVDSUnitClockGating:snb and
+	 * WaDisableRCCUnitClockGating:snb and
 	 * WaDisableRCPBUnitClockGating:snb.
 	 */
 	I915_WRITE(GEN6_UCGCTL2,
-- 
1.8.3.2

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Re: [PATCH 06/28] drm/i915: We implement WaDisableRCCUnitClockGating:snb

[Rodrigo Vivi]

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>

On Wed, Jan 22, 2014 at 5:32 PM,  <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index bbaf8c7..6a1d98a 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4606,6 +4606,7 @@ static void gen6_init_clock_gating(struct drm_device *dev)
>          * but we didn't debug actual testcases to find it out.
>          *
>          * Also apply WaDisableVDSUnitClockGating:snb and
> +        * WaDisableRCCUnitClockGating:snb and
>          * WaDisableRCPBUnitClockGating:snb.
>          */
>         I915_WRITE(GEN6_UCGCTL2,
> --
> 1.8.3.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br

[PATCH 07/28] drm/i915: We implement WaMiSetContext_Hang

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

WaMiSetContext_Hang tells us that a MI_NOOP must follow MI_SET_CONTEXT.

The other thing WaMiSetContext_Hang seems to say is that URB_FENCE isn't
allowed to straddle two cachelines. But we don't issue those from the
kernel so we don't care.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_gem_context.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
index 112f865..66edc84 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -573,7 +573,10 @@ mi_set_context(struct intel_ring_buffer *ring,
 			MI_SAVE_EXT_STATE_EN |
 			MI_RESTORE_EXT_STATE_EN |
 			hw_flags);
-	/* w/a: MI_SET_CONTEXT must always be followed by MI_NOOP */
+	/*
+	 * w/a: MI_SET_CONTEXT must always be followed by MI_NOOP
+	 * WaMiSetContext_Hang:snb,ivb,vlv
+	 */
 	intel_ring_emit(ring, MI_NOOP);
 
 	if (IS_GEN7(ring->dev))
-- 
1.8.3.2

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 07/28] drm/i915: We implement WaMiSetContext_Hang

[Rodrigo Vivi]

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>

On Wed, Jan 22, 2014 at 5:32 PM,  <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> WaMiSetContext_Hang tells us that a MI_NOOP must follow MI_SET_CONTEXT.
>
> The other thing WaMiSetContext_Hang seems to say is that URB_FENCE isn't
> allowed to straddle two cachelines. But we don't issue those from the
> kernel so we don't care.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_gem_context.c | 5 ++++-
>  1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
> index 112f865..66edc84 100644
> --- a/drivers/gpu/drm/i915/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/i915_gem_context.c
> @@ -573,7 +573,10 @@ mi_set_context(struct intel_ring_buffer *ring,
>                         MI_SAVE_EXT_STATE_EN |
>                         MI_RESTORE_EXT_STATE_EN |
>                         hw_flags);
> -       /* w/a: MI_SET_CONTEXT must always be followed by MI_NOOP */
> +       /*
> +        * w/a: MI_SET_CONTEXT must always be followed by MI_NOOP
> +        * WaMiSetContext_Hang:snb,ivb,vlv
> +        */
>         intel_ring_emit(ring, MI_NOOP);
>
>         if (IS_GEN7(ring->dev))
> --
> 1.8.3.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br

[PATCH 08/28] drm/i915: Fix IVB GT2 WaDisableDopClockGating and WaDisablePSDDualDispatchEnable

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

IVB GT2 has two registers for these things, and both must be written.

To add a bit more confusion both Bspec and the W/A database state that
WaDisablePSDDualDispatchEnable is only needed for IVB GT1, but the W/A
database also says to write even the second GT2 only register. So I
don't really know what the right thing here is.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 13 ++++++++++---
 1 file changed, 10 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 6a1d98a..b268a55 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4828,9 +4828,13 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
 	if (IS_IVB_GT1(dev))
 		I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
 			   _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
-	else
+	else {
+		/* must write both registers */
+		I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
+			   _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
 		I915_WRITE(GEN7_HALF_SLICE_CHICKEN1_GT2,
 			   _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
+	}
 
 	/* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
 	I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
@@ -4846,10 +4850,13 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
 	if (IS_IVB_GT1(dev))
 		I915_WRITE(GEN7_ROW_CHICKEN2,
 			   _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
-	else
+	else {
+		/* must write both registers */
+		I915_WRITE(GEN7_ROW_CHICKEN2,
+			   _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
 		I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
 			   _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
-
+	}
 
 	/* WaForceL3Serialization:ivb */
 	I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
-- 
1.8.3.2

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 08/28] drm/i915: Fix IVB GT2 WaDisableDopClockGating and WaDisablePSDDualDispatchEnable

[Rodrigo Vivi]

Your patch itself makes sense, but the registers values there are at i915_reg.h
differs from what I see at BSpec:

#define GEN7_ROW_CHICKEN2               0xe4f4
#define GEN7_ROW_CHICKEN2_GT2           0xf4f4

against
Address: 0E4F0h
Valid Projects: [DevIVB, EXCLUDE(DevIVB:GT2)]
Address: 0F4F0h
Valid Projects: [DevIVB:GT2]

Also, I couldn't see the wa description at wa_database...
description was empty for me..

On Wed, Jan 22, 2014 at 5:32 PM,  <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> IVB GT2 has two registers for these things, and both must be written.
>
> To add a bit more confusion both Bspec and the W/A database state that
> WaDisablePSDDualDispatchEnable is only needed for IVB GT1, but the W/A
> database also says to write even the second GT2 only register. So I
> don't really know what the right thing here is.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 13 ++++++++++---
>  1 file changed, 10 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 6a1d98a..b268a55 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4828,9 +4828,13 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
>         if (IS_IVB_GT1(dev))
>                 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
>                            _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
> -       else
> +       else {
> +               /* must write both registers */
> +               I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
> +                          _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
>                 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1_GT2,
>                            _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
> +       }
>
>         /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
>         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
> @@ -4846,10 +4850,13 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
>         if (IS_IVB_GT1(dev))
>                 I915_WRITE(GEN7_ROW_CHICKEN2,
>                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
> -       else
> +       else {
> +               /* must write both registers */
> +               I915_WRITE(GEN7_ROW_CHICKEN2,
> +                          _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
>                 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
>                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
> -
> +       }
>
>         /* WaForceL3Serialization:ivb */
>         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
> --
> 1.8.3.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br

Re: [PATCH 08/28] drm/i915: Fix IVB GT2 WaDisableDopClockGating and WaDisablePSDDualDispatchEnable

[Ville Syrjälä]

On Fri, Jan 24, 2014 at 03:32:08PM -0200, Rodrigo Vivi wrote:
> Your patch itself makes sense, but the registers values there are at i915_reg.h
> differs from what I see at BSpec:
> 
> #define GEN7_ROW_CHICKEN2               0xe4f4
> #define GEN7_ROW_CHICKEN2_GT2           0xf4f4
> 
> against
> Address: 0E4F0h
> Valid Projects: [DevIVB, EXCLUDE(DevIVB:GT2)]
> Address: 0F4F0h
> Valid Projects: [DevIVB:GT2]

ROW_CHICKEN vs. ROW_CHICKEN2

> 
> Also, I couldn't see the wa description at wa_database...
> description was empty for me..

Which one? WaDisableDopClockGating? It's not in the list for IVB,
so in order to see it you need to pick another platform which
includes this w/a.

> 
> On Wed, Jan 22, 2014 at 5:32 PM,  <ville.syrjala@linux.intel.com> wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > IVB GT2 has two registers for these things, and both must be written.
> >
> > To add a bit more confusion both Bspec and the W/A database state that
> > WaDisablePSDDualDispatchEnable is only needed for IVB GT1, but the W/A
> > database also says to write even the second GT2 only register. So I
> > don't really know what the right thing here is.
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_pm.c | 13 ++++++++++---
> >  1 file changed, 10 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index 6a1d98a..b268a55 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -4828,9 +4828,13 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
> >         if (IS_IVB_GT1(dev))
> >                 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
> >                            _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
> > -       else
> > +       else {
> > +               /* must write both registers */
> > +               I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
> > +                          _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
> >                 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1_GT2,
> >                            _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
> > +       }
> >
> >         /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
> >         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
> > @@ -4846,10 +4850,13 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
> >         if (IS_IVB_GT1(dev))
> >                 I915_WRITE(GEN7_ROW_CHICKEN2,
> >                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
> > -       else
> > +       else {
> > +               /* must write both registers */
> > +               I915_WRITE(GEN7_ROW_CHICKEN2,
> > +                          _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
> >                 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
> >                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
> > -
> > +       }
> >
> >         /* WaForceL3Serialization:ivb */
> >         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
> > --
> > 1.8.3.2
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> 
> 
> -- 
> Rodrigo Vivi
> Blog: http://blog.vivi.eng.br

-- 
Ville Syrjälä
Intel OTC

Re: [PATCH 08/28] drm/i915: Fix IVB GT2 WaDisableDopClockGating and WaDisablePSDDualDispatchEnable

[Rodrigo Vivi]

I agree that spec is strange, but following the spec correctly result
for this and next patch would be only this:

if (IS_IVB_GT1(dev))
  I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
    _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
- else
  I915_WRITE(GEN7_HALF_SLICE_CHICKEN1_GT2,
    _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
 }

On Fri, Jan 24, 2014 at 3:58 PM, Ville Syrjälä
<ville.syrjala@linux.intel.com> wrote:
> On Fri, Jan 24, 2014 at 03:32:08PM -0200, Rodrigo Vivi wrote:
>> Your patch itself makes sense, but the registers values there are at i915_reg.h
>> differs from what I see at BSpec:
>>
>> #define GEN7_ROW_CHICKEN2               0xe4f4
>> #define GEN7_ROW_CHICKEN2_GT2           0xf4f4
>>
>> against
>> Address: 0E4F0h
>> Valid Projects: [DevIVB, EXCLUDE(DevIVB:GT2)]
>> Address: 0F4F0h
>> Valid Projects: [DevIVB:GT2]
>
> ROW_CHICKEN vs. ROW_CHICKEN2
>
>>
>> Also, I couldn't see the wa description at wa_database...
>> description was empty for me..
>
> Which one? WaDisableDopClockGating? It's not in the list for IVB,
> so in order to see it you need to pick another platform which
> includes this w/a.
>
>>
>> On Wed, Jan 22, 2014 at 5:32 PM,  <ville.syrjala@linux.intel.com> wrote:
>> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> >
>> > IVB GT2 has two registers for these things, and both must be written.
>> >
>> > To add a bit more confusion both Bspec and the W/A database state that
>> > WaDisablePSDDualDispatchEnable is only needed for IVB GT1, but the W/A
>> > database also says to write even the second GT2 only register. So I
>> > don't really know what the right thing here is.
>> >
>> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> > ---
>> >  drivers/gpu/drm/i915/intel_pm.c | 13 ++++++++++---
>> >  1 file changed, 10 insertions(+), 3 deletions(-)
>> >
>> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
>> > index 6a1d98a..b268a55 100644
>> > --- a/drivers/gpu/drm/i915/intel_pm.c
>> > +++ b/drivers/gpu/drm/i915/intel_pm.c
>> > @@ -4828,9 +4828,13 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
>> >         if (IS_IVB_GT1(dev))
>> >                 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
>> >                            _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
>> > -       else
>> > +       else {
>> > +               /* must write both registers */
>> > +               I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
>> > +                          _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
>> >                 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1_GT2,
>> >                            _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
>> > +       }
>> >
>> >         /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
>> >         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
>> > @@ -4846,10 +4850,13 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
>> >         if (IS_IVB_GT1(dev))
>> >                 I915_WRITE(GEN7_ROW_CHICKEN2,
>> >                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
>> > -       else
>> > +       else {
>> > +               /* must write both registers */
>> > +               I915_WRITE(GEN7_ROW_CHICKEN2,
>> > +                          _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
>> >                 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
>> >                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
>> > -
>> > +       }
>> >
>> >         /* WaForceL3Serialization:ivb */
>> >         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
>> > --
>> > 1.8.3.2
>> >
>> > _______________________________________________
>> > Intel-gfx mailing list
>> > Intel-gfx@lists.freedesktop.org
>> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>>
>>
>>
>> --
>> Rodrigo Vivi
>> Blog: http://blog.vivi.eng.br
>
> --
> Ville Syrjälä
> Intel OTC



-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br

Re: [PATCH 08/28] drm/i915: Fix IVB GT2 WaDisableDopClockGating and WaDisablePSDDualDispatchEnable

[Ville Syrjälä]

On Tue, Jan 28, 2014 at 10:06:05AM -0200, Rodrigo Vivi wrote:
> I agree that spec is strange, but following the spec correctly result
> for this and next patch would be only this:
> 
> if (IS_IVB_GT1(dev))
>   I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
>     _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
> - else
>   I915_WRITE(GEN7_HALF_SLICE_CHICKEN1_GT2,
>     _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
>  }

That would match what the w/a database says. But bspec says otherwise.

But anyway Chris confirmed on his GT1 that GEN7_HALF_SLICE_CHICKEN1_GT2
doesn't exist there, so I think these patches are correct.

> 
> On Fri, Jan 24, 2014 at 3:58 PM, Ville Syrjälä
> <ville.syrjala@linux.intel.com> wrote:
> > On Fri, Jan 24, 2014 at 03:32:08PM -0200, Rodrigo Vivi wrote:
> >> Your patch itself makes sense, but the registers values there are at i915_reg.h
> >> differs from what I see at BSpec:
> >>
> >> #define GEN7_ROW_CHICKEN2               0xe4f4
> >> #define GEN7_ROW_CHICKEN2_GT2           0xf4f4
> >>
> >> against
> >> Address: 0E4F0h
> >> Valid Projects: [DevIVB, EXCLUDE(DevIVB:GT2)]
> >> Address: 0F4F0h
> >> Valid Projects: [DevIVB:GT2]
> >
> > ROW_CHICKEN vs. ROW_CHICKEN2
> >
> >>
> >> Also, I couldn't see the wa description at wa_database...
> >> description was empty for me..
> >
> > Which one? WaDisableDopClockGating? It's not in the list for IVB,
> > so in order to see it you need to pick another platform which
> > includes this w/a.
> >
> >>
> >> On Wed, Jan 22, 2014 at 5:32 PM,  <ville.syrjala@linux.intel.com> wrote:
> >> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >> >
> >> > IVB GT2 has two registers for these things, and both must be written.
> >> >
> >> > To add a bit more confusion both Bspec and the W/A database state that
> >> > WaDisablePSDDualDispatchEnable is only needed for IVB GT1, but the W/A
> >> > database also says to write even the second GT2 only register. So I
> >> > don't really know what the right thing here is.
> >> >
> >> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >> > ---
> >> >  drivers/gpu/drm/i915/intel_pm.c | 13 ++++++++++---
> >> >  1 file changed, 10 insertions(+), 3 deletions(-)
> >> >
> >> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> >> > index 6a1d98a..b268a55 100644
> >> > --- a/drivers/gpu/drm/i915/intel_pm.c
> >> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> >> > @@ -4828,9 +4828,13 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
> >> >         if (IS_IVB_GT1(dev))
> >> >                 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
> >> >                            _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
> >> > -       else
> >> > +       else {
> >> > +               /* must write both registers */
> >> > +               I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
> >> > +                          _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
> >> >                 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1_GT2,
> >> >                            _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
> >> > +       }
> >> >
> >> >         /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
> >> >         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
> >> > @@ -4846,10 +4850,13 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
> >> >         if (IS_IVB_GT1(dev))
> >> >                 I915_WRITE(GEN7_ROW_CHICKEN2,
> >> >                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
> >> > -       else
> >> > +       else {
> >> > +               /* must write both registers */
> >> > +               I915_WRITE(GEN7_ROW_CHICKEN2,
> >> > +                          _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
> >> >                 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
> >> >                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
> >> > -
> >> > +       }
> >> >
> >> >         /* WaForceL3Serialization:ivb */
> >> >         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
> >> > --
> >> > 1.8.3.2
> >> >
> >> > _______________________________________________
> >> > Intel-gfx mailing list
> >> > Intel-gfx@lists.freedesktop.org
> >> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> >>
> >>
> >>
> >> --
> >> Rodrigo Vivi
> >> Blog: http://blog.vivi.eng.br
> >
> > --
> > Ville Syrjälä
> > Intel OTC
> 
> 
> 
> -- 
> Rodrigo Vivi
> Blog: http://blog.vivi.eng.br

-- 
Ville Syrjälä
Intel OTC

Re: [PATCH 08/28] drm/i915: Fix IVB GT2 WaDisableDopClockGating and WaDisablePSDDualDispatchEnable

[Rodrigo Vivi]

Both registers must be programmed for the Mode bit to be valid. DevIVB:GT2 ...

So I also agree ;)
Maybe you should improve the commit message now that we are sure, but anyway:

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>

On Fri, Jan 31, 2014 at 4:28 AM, Ville Syrjälä
<ville.syrjala@linux.intel.com> wrote:
> On Tue, Jan 28, 2014 at 10:06:05AM -0200, Rodrigo Vivi wrote:
>> I agree that spec is strange, but following the spec correctly result
>> for this and next patch would be only this:
>>
>> if (IS_IVB_GT1(dev))
>>   I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
>>     _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
>> - else
>>   I915_WRITE(GEN7_HALF_SLICE_CHICKEN1_GT2,
>>     _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
>>  }
>
> That would match what the w/a database says. But bspec says otherwise.
>
> But anyway Chris confirmed on his GT1 that GEN7_HALF_SLICE_CHICKEN1_GT2
> doesn't exist there, so I think these patches are correct.
>
>>
>> On Fri, Jan 24, 2014 at 3:58 PM, Ville Syrjälä
>> <ville.syrjala@linux.intel.com> wrote:
>> > On Fri, Jan 24, 2014 at 03:32:08PM -0200, Rodrigo Vivi wrote:
>> >> Your patch itself makes sense, but the registers values there are at i915_reg.h
>> >> differs from what I see at BSpec:
>> >>
>> >> #define GEN7_ROW_CHICKEN2               0xe4f4
>> >> #define GEN7_ROW_CHICKEN2_GT2           0xf4f4
>> >>
>> >> against
>> >> Address: 0E4F0h
>> >> Valid Projects: [DevIVB, EXCLUDE(DevIVB:GT2)]
>> >> Address: 0F4F0h
>> >> Valid Projects: [DevIVB:GT2]
>> >
>> > ROW_CHICKEN vs. ROW_CHICKEN2
>> >
>> >>
>> >> Also, I couldn't see the wa description at wa_database...
>> >> description was empty for me..
>> >
>> > Which one? WaDisableDopClockGating? It's not in the list for IVB,
>> > so in order to see it you need to pick another platform which
>> > includes this w/a.
>> >
>> >>
>> >> On Wed, Jan 22, 2014 at 5:32 PM,  <ville.syrjala@linux.intel.com> wrote:
>> >> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> >> >
>> >> > IVB GT2 has two registers for these things, and both must be written.
>> >> >
>> >> > To add a bit more confusion both Bspec and the W/A database state that
>> >> > WaDisablePSDDualDispatchEnable is only needed for IVB GT1, but the W/A
>> >> > database also says to write even the second GT2 only register. So I
>> >> > don't really know what the right thing here is.
>> >> >
>> >> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> >> > ---
>> >> >  drivers/gpu/drm/i915/intel_pm.c | 13 ++++++++++---
>> >> >  1 file changed, 10 insertions(+), 3 deletions(-)
>> >> >
>> >> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
>> >> > index 6a1d98a..b268a55 100644
>> >> > --- a/drivers/gpu/drm/i915/intel_pm.c
>> >> > +++ b/drivers/gpu/drm/i915/intel_pm.c
>> >> > @@ -4828,9 +4828,13 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
>> >> >         if (IS_IVB_GT1(dev))
>> >> >                 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
>> >> >                            _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
>> >> > -       else
>> >> > +       else {
>> >> > +               /* must write both registers */
>> >> > +               I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
>> >> > +                          _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
>> >> >                 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1_GT2,
>> >> >                            _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
>> >> > +       }
>> >> >
>> >> >         /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
>> >> >         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
>> >> > @@ -4846,10 +4850,13 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
>> >> >         if (IS_IVB_GT1(dev))
>> >> >                 I915_WRITE(GEN7_ROW_CHICKEN2,
>> >> >                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
>> >> > -       else
>> >> > +       else {
>> >> > +               /* must write both registers */
>> >> > +               I915_WRITE(GEN7_ROW_CHICKEN2,
>> >> > +                          _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
>> >> >                 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
>> >> >                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
>> >> > -
>> >> > +       }
>> >> >
>> >> >         /* WaForceL3Serialization:ivb */
>> >> >         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
>> >> > --
>> >> > 1.8.3.2
>> >> >
>> >> > _______________________________________________
>> >> > Intel-gfx mailing list
>> >> > Intel-gfx@lists.freedesktop.org
>> >> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>> >>
>> >>
>> >>
>> >> --
>> >> Rodrigo Vivi
>> >> Blog: http://blog.vivi.eng.br
>> >
>> > --
>> > Ville Syrjälä
>> > Intel OTC
>>
>>
>>
>> --
>> Rodrigo Vivi
>> Blog: http://blog.vivi.eng.br
>
> --
> Ville Syrjälä
> Intel OTC



-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br

Re: [PATCH 08/28] drm/i915: Fix IVB GT2 WaDisableDopClockGating and WaDisablePSDDualDispatchEnable

[Daniel Vetter]

On Fri, Jan 31, 2014 at 08:05:37AM -0500, Rodrigo Vivi wrote:
> Both registers must be programmed for the Mode bit to be valid. DevIVB:GT2 ...
> 
> So I also agree ;)
> Maybe you should improve the commit message now that we are sure, but anyway:

I've added a little not to the commit message when merging, thanks for
figuring this all out.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

[PATCH 09/28] drm/i915: Drop WaDisablePSDDualDispatchEnable:ivb for IVB GT2

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Both Bspec and the W/A database state that WaDisablePSDDualDispatchEnable
is only needed for IVB GT1.

The only real confusion here is that the the W/A database also says to
write to the GT2 only register as well, which is strange if the W/A is
only for GT1.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 7 -------
 1 file changed, 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index b268a55..6781845 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4828,13 +4828,6 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
 	if (IS_IVB_GT1(dev))
 		I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
 			   _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
-	else {
-		/* must write both registers */
-		I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
-			   _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
-		I915_WRITE(GEN7_HALF_SLICE_CHICKEN1_GT2,
-			   _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
-	}
 
 	/* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
 	I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
-- 
1.8.3.2

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 09/28] drm/i915: Drop WaDisablePSDDualDispatchEnable:ivb for IVB GT2

[Rodrigo Vivi]

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>

I think this was the last wa patch to be reviewed yet. Please let me
know if I' m still missing any.


On Wed, Jan 22, 2014 at 2:32 PM,  <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Both Bspec and the W/A database state that WaDisablePSDDualDispatchEnable
> is only needed for IVB GT1.
>
> The only real confusion here is that the the W/A database also says to
> write to the GT2 only register as well, which is strange if the W/A is
> only for GT1.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 7 -------
>  1 file changed, 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index b268a55..6781845 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4828,13 +4828,6 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
>         if (IS_IVB_GT1(dev))
>                 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
>                            _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
> -       else {
> -               /* must write both registers */
> -               I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
> -                          _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
> -               I915_WRITE(GEN7_HALF_SLICE_CHICKEN1_GT2,
> -                          _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
> -       }
>
>         /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
>         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
> --
> 1.8.3.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br

[PATCH 10/28] drm/i915: Implement WaIncreaseL3CreditsForVLVB0:vlv

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 3 +++
 drivers/gpu/drm/i915/intel_pm.c | 6 ++++++
 2 files changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 242f540..c3039e1 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4126,6 +4126,9 @@
 #define COMMON_SLICE_CHICKEN2			0x7014
 # define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE	(1<<0)
 
+#define GEN7_L3SQCREG1				0xB010
+#define  VLV_B0_WA_L3SQCREG1_VALUE		0x00D30000
+
 #define GEN7_L3CNTLREG1				0xB01C
 #define  GEN7_WA_FOR_GEN7_L3_CONTROL			0x3C4FFF8C
 #define  GEN7_L3AGDIS				(1<<19)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 6781845..4a1f849 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4992,6 +4992,12 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
 		   _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
 
 	/*
+	 * WaIncreaseL3CreditsForVLVB0:vlv
+	 * This is the hardware default actually.
+	 */
+	I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
+
+	/*
 	 * WaDisableVLVClockGating_VBIIssue:vlv
 	 * Disable clock gating on th GCFG unit to prevent a delay
 	 * in the reporting of vblank events.
-- 
1.8.3.2

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 10/28] drm/i915: Implement WaIncreaseL3CreditsForVLVB0:vlv

[Rodrigo Vivi]

On Wed, Jan 22, 2014 at 5:32 PM,  <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h | 3 +++
>  drivers/gpu/drm/i915/intel_pm.c | 6 ++++++
>  2 files changed, 9 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 242f540..c3039e1 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4126,6 +4126,9 @@
>  #define COMMON_SLICE_CHICKEN2                  0x7014
>  # define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE  (1<<0)
>
> +#define GEN7_L3SQCREG1                         0xB010
> +#define  VLV_B0_WA_L3SQCREG1_VALUE             0x00D30000

where did you get this value?
All I see on wa_database was "L3Sqc Register will be having a
different value from VLVB0."
so I wonder if I'm looking to a different and wrong place.
please point me to the correct one

> +
>  #define GEN7_L3CNTLREG1                                0xB01C
>  #define  GEN7_WA_FOR_GEN7_L3_CONTROL                   0x3C4FFF8C
>  #define  GEN7_L3AGDIS                          (1<<19)
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 6781845..4a1f849 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4992,6 +4992,12 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
>                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
>
>         /*
> +        * WaIncreaseL3CreditsForVLVB0:vlv
> +        * This is the hardware default actually.
> +        */
> +       I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
> +
> +       /*
>          * WaDisableVLVClockGating_VBIIssue:vlv
>          * Disable clock gating on th GCFG unit to prevent a delay
>          * in the reporting of vblank events.
> --
> 1.8.3.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br

Re: [PATCH 10/28] drm/i915: Implement WaIncreaseL3CreditsForVLVB0:vlv

[Rodrigo Vivi]

Thanks for the clarification: Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>

On Tue, Jan 28, 2014 at 10:11 AM, Rodrigo Vivi <rodrigo.vivi@gmail.com> wrote:
> On Wed, Jan 22, 2014 at 5:32 PM,  <ville.syrjala@linux.intel.com> wrote:
>> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>
>> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> ---
>>  drivers/gpu/drm/i915/i915_reg.h | 3 +++
>>  drivers/gpu/drm/i915/intel_pm.c | 6 ++++++
>>  2 files changed, 9 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index 242f540..c3039e1 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -4126,6 +4126,9 @@
>>  #define COMMON_SLICE_CHICKEN2                  0x7014
>>  # define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE  (1<<0)
>>
>> +#define GEN7_L3SQCREG1                         0xB010
>> +#define  VLV_B0_WA_L3SQCREG1_VALUE             0x00D30000
>
> where did you get this value?
> All I see on wa_database was "L3Sqc Register will be having a
> different value from VLVB0."
> so I wonder if I'm looking to a different and wrong place.
> please point me to the correct one
>
>> +
>>  #define GEN7_L3CNTLREG1                                0xB01C
>>  #define  GEN7_WA_FOR_GEN7_L3_CONTROL                   0x3C4FFF8C
>>  #define  GEN7_L3AGDIS                          (1<<19)
>> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
>> index 6781845..4a1f849 100644
>> --- a/drivers/gpu/drm/i915/intel_pm.c
>> +++ b/drivers/gpu/drm/i915/intel_pm.c
>> @@ -4992,6 +4992,12 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
>>                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
>>
>>         /*
>> +        * WaIncreaseL3CreditsForVLVB0:vlv
>> +        * This is the hardware default actually.
>> +        */
>> +       I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
>> +
>> +       /*
>>          * WaDisableVLVClockGating_VBIIssue:vlv
>>          * Disable clock gating on th GCFG unit to prevent a delay
>>          * in the reporting of vblank events.
>> --
>> 1.8.3.2
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
>
>
> --
> Rodrigo Vivi
> Blog: http://blog.vivi.eng.br



-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br

[PATCH 11/28] drm/i915: WaDisableVDSUnitClockGating isn't applicable to SNB

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Can't find any mention of WaDisableVDSUnitClockGating ever being
relevant for SNB. Remove it.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 4a1f849..f40dd1b 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4605,12 +4605,10 @@ static void gen6_init_clock_gating(struct drm_device *dev)
 	 * According to the spec, bit 11 (RCCUNIT) must also be set,
 	 * but we didn't debug actual testcases to find it out.
 	 *
-	 * Also apply WaDisableVDSUnitClockGating:snb and
-	 * WaDisableRCCUnitClockGating:snb and
-	 * WaDisableRCPBUnitClockGating:snb.
+	 * WaDisableRCCUnitClockGating:snb
+	 * WaDisableRCPBUnitClockGating:snb
 	 */
 	I915_WRITE(GEN6_UCGCTL2,
-		   GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
 		   GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
 		   GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
 
-- 
1.8.3.2

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Re: [PATCH 11/28] drm/i915: WaDisableVDSUnitClockGating isn't applicable to SNB

[Rodrigo Vivi]

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>

On Wed, Jan 22, 2014 at 5:32 PM,  <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Can't find any mention of WaDisableVDSUnitClockGating ever being
> relevant for SNB. Remove it.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 6 ++----
>  1 file changed, 2 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 4a1f849..f40dd1b 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4605,12 +4605,10 @@ static void gen6_init_clock_gating(struct drm_device *dev)
>          * According to the spec, bit 11 (RCCUNIT) must also be set,
>          * but we didn't debug actual testcases to find it out.
>          *
> -        * Also apply WaDisableVDSUnitClockGating:snb and
> -        * WaDisableRCCUnitClockGating:snb and
> -        * WaDisableRCPBUnitClockGating:snb.
> +        * WaDisableRCCUnitClockGating:snb
> +        * WaDisableRCPBUnitClockGating:snb
>          */
>         I915_WRITE(GEN6_UCGCTL2,
> -                  GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
>                    GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
>                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
>
> --
> 1.8.3.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br

[PATCH 12/28] drm/i915: WaDisableRCCUnitClockGating isn't applicable to IVB

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

WaDisableRCCUnitClockGating is only relevant for SNB.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 6 +-----
 1 file changed, 1 insertion(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index f40dd1b..1e1c1b1 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4860,15 +4860,11 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
 	 * Sanctuary and Tropics, and apparently anything else with
 	 * alpha test or pixel discard.
 	 *
-	 * According to the spec, bit 11 (RCCUNIT) must also be set,
-	 * but we didn't debug actual testcases to find it out.
-	 *
 	 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
 	 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
 	 */
 	I915_WRITE(GEN6_UCGCTL2,
-		   GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
-		   GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
+		   GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
 
 	/* This is required by WaCatErrorRejectionIssue:ivb */
 	I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
-- 
1.8.3.2

_______________________________________________
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http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 12/28] drm/i915: WaDisableRCCUnitClockGating isn't applicable to IVB

[Rodrigo Vivi]

For this and next one: According to wa_database this wa seems relevant
for all gt, right?

On Wed, Jan 22, 2014 at 5:32 PM,  <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> WaDisableRCCUnitClockGating is only relevant for SNB.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 6 +-----
>  1 file changed, 1 insertion(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index f40dd1b..1e1c1b1 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4860,15 +4860,11 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
>          * Sanctuary and Tropics, and apparently anything else with
>          * alpha test or pixel discard.
>          *
> -        * According to the spec, bit 11 (RCCUNIT) must also be set,
> -        * but we didn't debug actual testcases to find it out.
> -        *
>          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
>          * This implements the WaDisableRCZUnitClockGating:ivb workaround.
>          */
>         I915_WRITE(GEN6_UCGCTL2,
> -                  GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
> -                  GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
> +                  GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
>
>         /* This is required by WaCatErrorRejectionIssue:ivb */
>         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
> --
> 1.8.3.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br

Re: [PATCH 12/28] drm/i915: WaDisableRCCUnitClockGating isn't applicable to IVB

[Ville Syrjälä]

On Tue, Jan 28, 2014 at 10:18:48AM -0200, Rodrigo Vivi wrote:
> For this and next one: According to wa_database this wa seems relevant
> for all gt, right?

snb is called gt in w/a database language, or did you mean something else?

> 
> On Wed, Jan 22, 2014 at 5:32 PM,  <ville.syrjala@linux.intel.com> wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > WaDisableRCCUnitClockGating is only relevant for SNB.
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_pm.c | 6 +-----
> >  1 file changed, 1 insertion(+), 5 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index f40dd1b..1e1c1b1 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -4860,15 +4860,11 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
> >          * Sanctuary and Tropics, and apparently anything else with
> >          * alpha test or pixel discard.
> >          *
> > -        * According to the spec, bit 11 (RCCUNIT) must also be set,
> > -        * but we didn't debug actual testcases to find it out.
> > -        *
> >          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
> >          * This implements the WaDisableRCZUnitClockGating:ivb workaround.
> >          */
> >         I915_WRITE(GEN6_UCGCTL2,
> > -                  GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
> > -                  GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
> > +                  GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
> >
> >         /* This is required by WaCatErrorRejectionIssue:ivb */
> >         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
> > --
> > 1.8.3.2
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> 
> 
> -- 
> Rodrigo Vivi
> Blog: http://blog.vivi.eng.br

-- 
Ville Syrjälä
Intel OTC

Re: [PATCH 12/28] drm/i915: WaDisableRCCUnitClockGating isn't applicable to IVB

[Rodrigo Vivi]

Nope, I had misunderstood that definition.. Thanks for the clarification.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>

On Tue, Jan 28, 2014 at 10:29 AM, Ville Syrjälä
<ville.syrjala@linux.intel.com> wrote:
> On Tue, Jan 28, 2014 at 10:18:48AM -0200, Rodrigo Vivi wrote:
>> For this and next one: According to wa_database this wa seems relevant
>> for all gt, right?
>
> snb is called gt in w/a database language, or did you mean something else?
>
>>
>> On Wed, Jan 22, 2014 at 5:32 PM,  <ville.syrjala@linux.intel.com> wrote:
>> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> >
>> > WaDisableRCCUnitClockGating is only relevant for SNB.
>> >
>> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> > ---
>> >  drivers/gpu/drm/i915/intel_pm.c | 6 +-----
>> >  1 file changed, 1 insertion(+), 5 deletions(-)
>> >
>> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
>> > index f40dd1b..1e1c1b1 100644
>> > --- a/drivers/gpu/drm/i915/intel_pm.c
>> > +++ b/drivers/gpu/drm/i915/intel_pm.c
>> > @@ -4860,15 +4860,11 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
>> >          * Sanctuary and Tropics, and apparently anything else with
>> >          * alpha test or pixel discard.
>> >          *
>> > -        * According to the spec, bit 11 (RCCUNIT) must also be set,
>> > -        * but we didn't debug actual testcases to find it out.
>> > -        *
>> >          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
>> >          * This implements the WaDisableRCZUnitClockGating:ivb workaround.
>> >          */
>> >         I915_WRITE(GEN6_UCGCTL2,
>> > -                  GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
>> > -                  GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
>> > +                  GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
>> >
>> >         /* This is required by WaCatErrorRejectionIssue:ivb */
>> >         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
>> > --
>> > 1.8.3.2
>> >
>> > _______________________________________________
>> > Intel-gfx mailing list
>> > Intel-gfx@lists.freedesktop.org
>> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>>
>>
>>
>> --
>> Rodrigo Vivi
>> Blog: http://blog.vivi.eng.br
>
> --
> Ville Syrjälä
> Intel OTC



-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br

[PATCH 13/28] drm/i915: WaDisableRCCUnitClockGating isn't applicaple to VLV

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

WaDisableRCCUnitClockGating is only relevant for SNB.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 6 +-----
 1 file changed, 1 insertion(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 1e1c1b1..d8381b5 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4961,9 +4961,6 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
 	 * Sanctuary and Tropics, and apparently anything else with
 	 * alpha test or pixel discard.
 	 *
-	 * According to the spec, bit 11 (RCCUNIT) must also be set,
-	 * but we didn't debug actual testcases to find it out.
-	 *
 	 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
 	 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
 	 *
@@ -4974,8 +4971,7 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
 		   GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
 		   GEN7_TDLUNIT_CLOCK_GATE_DISABLE |
 		   GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
-		   GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
-		   GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
+		   GEN6_RCPBUNIT_CLOCK_GATE_DISABLE);
 
 	/* WaDisableL3Bank2xClockGate:vlv */
 	I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
-- 
1.8.3.2

_______________________________________________
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http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 13/28] drm/i915: WaDisableRCCUnitClockGating isn't applicaple to VLV

[Rodrigo Vivi]

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>

On Wed, Jan 22, 2014 at 5:32 PM,  <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> WaDisableRCCUnitClockGating is only relevant for SNB.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 6 +-----
>  1 file changed, 1 insertion(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 1e1c1b1..d8381b5 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4961,9 +4961,6 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
>          * Sanctuary and Tropics, and apparently anything else with
>          * alpha test or pixel discard.
>          *
> -        * According to the spec, bit 11 (RCCUNIT) must also be set,
> -        * but we didn't debug actual testcases to find it out.
> -        *
>          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
>          * This implements the WaDisableRCZUnitClockGating:vlv workaround.
>          *
> @@ -4974,8 +4971,7 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
>                    GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
>                    GEN7_TDLUNIT_CLOCK_GATE_DISABLE |
>                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
> -                  GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
> -                  GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
> +                  GEN6_RCPBUNIT_CLOCK_GATE_DISABLE);
>
>         /* WaDisableL3Bank2xClockGate:vlv */
>         I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
> --
> 1.8.3.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br

[PATCH 14/28] drm/i915: WaDisableRHWOOptimizationForRenderHang isn't applicable to HSW

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Can't find WaDisableRHWOOptimizationForRenderHang listed for HSW.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 4 ----
 1 file changed, 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index d8381b5..f9c44d2 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4767,10 +4767,6 @@ static void haswell_init_clock_gating(struct drm_device *dev)
 	 */
 	I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
 
-	/* Apply the WaDisableRHWOOptimizationForRenderHang:hsw workaround. */
-	I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
-		   GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
-
 	/* WaApplyL3ControlAndL3ChickenMode:hsw */
 	I915_WRITE(GEN7_L3CNTLREG1,
 			GEN7_WA_FOR_GEN7_L3_CONTROL);
-- 
1.8.3.2

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Re: [PATCH 14/28] drm/i915: WaDisableRHWOOptimizationForRenderHang isn't applicable to HSW

[Rodrigo Vivi]

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>

On Wed, Jan 22, 2014 at 5:32 PM,  <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Can't find WaDisableRHWOOptimizationForRenderHang listed for HSW.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 4 ----
>  1 file changed, 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index d8381b5..f9c44d2 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4767,10 +4767,6 @@ static void haswell_init_clock_gating(struct drm_device *dev)
>          */
>         I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
>
> -       /* Apply the WaDisableRHWOOptimizationForRenderHang:hsw workaround. */
> -       I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
> -                  GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
> -
>         /* WaApplyL3ControlAndL3ChickenMode:hsw */
>         I915_WRITE(GEN7_L3CNTLREG1,
>                         GEN7_WA_FOR_GEN7_L3_CONTROL);
> --
> 1.8.3.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br

[PATCH 15/28] drm/i915: WaDisableRHWOOptimizationForRenderHang isn't applicable to VLV

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Can't find WaDisableRHWOOptimizationForRenderHang listed for VLV.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 4 ----
 1 file changed, 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index f9c44d2..895046f 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4928,10 +4928,6 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
 		   _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
 				      GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
 
-	/* Apply the WaDisableRHWOOptimizationForRenderHang:vlv workaround. */
-	I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
-		   GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
-
 	/* WaDisableL3CacheAging:vlv */
 	I915_WRITE(GEN7_L3CNTLREG1, I915_READ(GEN7_L3CNTLREG1) | GEN7_L3AGDIS);
 	/* WaApplyL3ControlAndL3ChickenMode:vlv */
-- 
1.8.3.2

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http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 15/28] drm/i915: WaDisableRHWOOptimizationForRenderHang isn't applicable to VLV

[Rodrigo Vivi]

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>

On Wed, Jan 22, 2014 at 5:32 PM,  <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Can't find WaDisableRHWOOptimizationForRenderHang listed for VLV.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 4 ----
>  1 file changed, 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index f9c44d2..895046f 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4928,10 +4928,6 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
>                    _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
>                                       GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
>
> -       /* Apply the WaDisableRHWOOptimizationForRenderHang:vlv workaround. */
> -       I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
> -                  GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
> -
>         /* WaDisableL3CacheAging:vlv */
>         I915_WRITE(GEN7_L3CNTLREG1, I915_READ(GEN7_L3CNTLREG1) | GEN7_L3AGDIS);
>         /* WaApplyL3ControlAndL3ChickenMode:vlv */
> --
> 1.8.3.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br

[PATCH 16/28] drm/i915: WaApplyL3ControlAndL3ChickenMode isn't applicable for VLV

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

WaApplyL3ControlAndL3ChickenMode is only listed for IVB and HSW in
W/A database and BSpec.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 895046f..62d339b 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4930,8 +4930,6 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
 
 	/* WaDisableL3CacheAging:vlv */
 	I915_WRITE(GEN7_L3CNTLREG1, I915_READ(GEN7_L3CNTLREG1) | GEN7_L3AGDIS);
-	/* WaApplyL3ControlAndL3ChickenMode:vlv */
-	I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE);
 
 	/* WaForceL3Serialization:vlv */
 	I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
-- 
1.8.3.2

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http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 16/28] drm/i915: WaApplyL3ControlAndL3ChickenMode isn't applicable for VLV

[Rodrigo Vivi]

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>

On Wed, Jan 22, 2014 at 5:32 PM,  <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> WaApplyL3ControlAndL3ChickenMode is only listed for IVB and HSW in
> W/A database and BSpec.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 2 --
>  1 file changed, 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 895046f..62d339b 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4930,8 +4930,6 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
>
>         /* WaDisableL3CacheAging:vlv */
>         I915_WRITE(GEN7_L3CNTLREG1, I915_READ(GEN7_L3CNTLREG1) | GEN7_L3AGDIS);
> -       /* WaApplyL3ControlAndL3ChickenMode:vlv */
> -       I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE);
>
>         /* WaForceL3Serialization:vlv */
>         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
> --
> 1.8.3.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br

Re: [PATCH 16/28] drm/i915: WaApplyL3ControlAndL3ChickenMode isn't applicable for VLV

[Daniel Vetter]

On Wed, Jan 22, 2014 at 09:32:52PM +0200, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> WaApplyL3ControlAndL3ChickenMode is only listed for IVB and HSW in
> W/A database and BSpec.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 2 --
>  1 file changed, 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 895046f..62d339b 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4930,8 +4930,6 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
>  
>  	/* WaDisableL3CacheAging:vlv */
>  	I915_WRITE(GEN7_L3CNTLREG1, I915_READ(GEN7_L3CNTLREG1) | GEN7_L3AGDIS);
> -	/* WaApplyL3ControlAndL3ChickenMode:vlv */
> -	I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE);

This one doesn't seem to be here ... is some earlier patch which I haven't
merged yet adding this? Can't we just fold this in?
-Daniel

>  
>  	/* WaForceL3Serialization:vlv */
>  	I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
> -- 
> 1.8.3.2
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH 16/28] drm/i915: WaApplyL3ControlAndL3ChickenMode isn't applicable for VLV

[Ville Syrjälä]

On Tue, Jan 28, 2014 at 02:24:42PM +0100, Daniel Vetter wrote:
> On Wed, Jan 22, 2014 at 09:32:52PM +0200, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > WaApplyL3ControlAndL3ChickenMode is only listed for IVB and HSW in
> > W/A database and BSpec.
> > 
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_pm.c | 2 --
> >  1 file changed, 2 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index 895046f..62d339b 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -4930,8 +4930,6 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
> >  
> >  	/* WaDisableL3CacheAging:vlv */
> >  	I915_WRITE(GEN7_L3CNTLREG1, I915_READ(GEN7_L3CNTLREG1) | GEN7_L3AGDIS);
> > -	/* WaApplyL3ControlAndL3ChickenMode:vlv */
> > -	I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE);
> 
> This one doesn't seem to be here ... is some earlier patch which I haven't
> merged yet adding this? Can't we just fold this in?

? I see you alreay applied this patch. Are ou trying to put it in twice?
IIRC in the past we applied one workaround three times, now we're trying
to not apply one twice :)

> -Daniel
> 
> >  
> >  	/* WaForceL3Serialization:vlv */
> >  	I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
> > -- 
> > 1.8.3.2
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> -- 
> Daniel Vetter
> Software Engineer, Intel Corporation
> +41 (0) 79 365 57 48 - http://blog.ffwll.ch

-- 
Ville Syrjälä
Intel OTC

Re: [PATCH 16/28] drm/i915: WaApplyL3ControlAndL3ChickenMode isn't applicable for VLV

[Daniel Vetter]

On Tue, Jan 28, 2014 at 04:13:52PM +0200, Ville Syrjälä wrote:
> On Tue, Jan 28, 2014 at 02:24:42PM +0100, Daniel Vetter wrote:
> > On Wed, Jan 22, 2014 at 09:32:52PM +0200, ville.syrjala@linux.intel.com wrote:
> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > 
> > > WaApplyL3ControlAndL3ChickenMode is only listed for IVB and HSW in
> > > W/A database and BSpec.
> > > 
> > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/intel_pm.c | 2 --
> > >  1 file changed, 2 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > > index 895046f..62d339b 100644
> > > --- a/drivers/gpu/drm/i915/intel_pm.c
> > > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > > @@ -4930,8 +4930,6 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
> > >  
> > >  	/* WaDisableL3CacheAging:vlv */
> > >  	I915_WRITE(GEN7_L3CNTLREG1, I915_READ(GEN7_L3CNTLREG1) | GEN7_L3AGDIS);
> > > -	/* WaApplyL3ControlAndL3ChickenMode:vlv */
> > > -	I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE);
> > 
> > This one doesn't seem to be here ... is some earlier patch which I haven't
> > merged yet adding this? Can't we just fold this in?
> 
> ? I see you alreay applied this patch. Are ou trying to put it in twice?
> IIRC in the past we applied one workaround three times, now we're trying
> to not apply one twice :)

Oh right, Rodrigo reviewed this one yesterday already. Sorry for the
confusion ;-)
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

[PATCH 17/28] drm/i915: Drop bogus comment about RCPB unit clock gating on IVB

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Someone copy pasted the comment from the SNB code w/o reading it.
We never actually implemented the workaround to disable RCPB unit
clock gating on IVB. It would have been needed for early steppings,
but we don't care about those anymore, so just remove the stale
comment.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 8 +-------
 1 file changed, 1 insertion(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 62d339b..bf45b4c 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4849,13 +4849,7 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
 	I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
 		   ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
 
-	/* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
-	 * gating disable must be set.  Failure to set it results in
-	 * flickering pixels due to Z write ordering failures after
-	 * some amount of runtime in the Mesa "fire" demo, and Unigine
-	 * Sanctuary and Tropics, and apparently anything else with
-	 * alpha test or pixel discard.
-	 *
+	/*
 	 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
 	 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
 	 */
-- 
1.8.3.2

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http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 17/28] drm/i915: Drop bogus comment about RCPB unit clock gating on IVB

[Rodrigo Vivi]

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>

On Wed, Jan 22, 2014 at 5:32 PM,  <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Someone copy pasted the comment from the SNB code w/o reading it.
> We never actually implemented the workaround to disable RCPB unit
> clock gating on IVB. It would have been needed for early steppings,
> but we don't care about those anymore, so just remove the stale
> comment.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 8 +-------
>  1 file changed, 1 insertion(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 62d339b..bf45b4c 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4849,13 +4849,7 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
>         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
>                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
>
> -       /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
> -        * gating disable must be set.  Failure to set it results in
> -        * flickering pixels due to Z write ordering failures after
> -        * some amount of runtime in the Mesa "fire" demo, and Unigine
> -        * Sanctuary and Tropics, and apparently anything else with
> -        * alpha test or pixel discard.
> -        *
> +       /*
>          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
>          * This implements the WaDisableRCZUnitClockGating:ivb workaround.
>          */
> --
> 1.8.3.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br

[PATCH 18/28] drm/i915: Drop WaDisableRCZUnitClockGating:hsw

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

WaDisableRCZUnitClockGating was needed with early HSW steppings only.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 5 -----
 1 file changed, 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index bf45b4c..70f3b2b 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4762,11 +4762,6 @@ static void haswell_init_clock_gating(struct drm_device *dev)
 
 	ilk_init_lp_watermarks(dev);
 
-	/* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
-	 * This implements the WaDisableRCZUnitClockGating:hsw workaround.
-	 */
-	I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
-
 	/* WaApplyL3ControlAndL3ChickenMode:hsw */
 	I915_WRITE(GEN7_L3CNTLREG1,
 			GEN7_WA_FOR_GEN7_L3_CONTROL);
-- 
1.8.3.2

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http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 18/28] drm/i915: Drop WaDisableRCZUnitClockGating:hsw

[Rodrigo Vivi]

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>

On Wed, Jan 22, 2014 at 5:32 PM,  <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> WaDisableRCZUnitClockGating was needed with early HSW steppings only.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 5 -----
>  1 file changed, 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index bf45b4c..70f3b2b 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4762,11 +4762,6 @@ static void haswell_init_clock_gating(struct drm_device *dev)
>
>         ilk_init_lp_watermarks(dev);
>
> -       /* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
> -        * This implements the WaDisableRCZUnitClockGating:hsw workaround.
> -        */
> -       I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
> -
>         /* WaApplyL3ControlAndL3ChickenMode:hsw */
>         I915_WRITE(GEN7_L3CNTLREG1,
>                         GEN7_WA_FOR_GEN7_L3_CONTROL);
> --
> 1.8.3.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br

Re: [PATCH 18/28] drm/i915: Drop WaDisableRCZUnitClockGating:hsw

[Daniel Vetter]

On Wed, Jan 22, 2014 at 09:32:54PM +0200, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> WaDisableRCZUnitClockGating was needed with early HSW steppings only.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

I couldn't make sense of this diff, my hsw clock_gating function here
doesn't seem to have this hunk?!
-Daniel

> ---
>  drivers/gpu/drm/i915/intel_pm.c | 5 -----
>  1 file changed, 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index bf45b4c..70f3b2b 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4762,11 +4762,6 @@ static void haswell_init_clock_gating(struct drm_device *dev)
>  
>  	ilk_init_lp_watermarks(dev);
>  
> -	/* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
> -	 * This implements the WaDisableRCZUnitClockGating:hsw workaround.
> -	 */
> -	I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
> -
>  	/* WaApplyL3ControlAndL3ChickenMode:hsw */
>  	I915_WRITE(GEN7_L3CNTLREG1,
>  			GEN7_WA_FOR_GEN7_L3_CONTROL);
> -- 
> 1.8.3.2
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

[PATCH 19/28] drm/i915: Drop WaApplyL3ControlAndL3ChickenMode:hsw

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

WaApplyL3ControlAndL3ChickenMode is only relevant to early HSW
steppings..

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 6 ------
 1 file changed, 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 70f3b2b..0d9ded4 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4762,12 +4762,6 @@ static void haswell_init_clock_gating(struct drm_device *dev)
 
 	ilk_init_lp_watermarks(dev);
 
-	/* WaApplyL3ControlAndL3ChickenMode:hsw */
-	I915_WRITE(GEN7_L3CNTLREG1,
-			GEN7_WA_FOR_GEN7_L3_CONTROL);
-	I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
-			GEN7_WA_L3_CHICKEN_MODE);
-
 	/* L3 caching of data atomics doesn't work -- disable it. */
 	I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
 	I915_WRITE(HSW_ROW_CHICKEN3,
-- 
1.8.3.2

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Re: [PATCH 19/28] drm/i915: Drop WaApplyL3ControlAndL3ChickenMode:hsw

[Rodrigo Vivi]

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>

On Wed, Jan 22, 2014 at 5:32 PM,  <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> WaApplyL3ControlAndL3ChickenMode is only relevant to early HSW
> steppings..
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 6 ------
>  1 file changed, 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 70f3b2b..0d9ded4 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4762,12 +4762,6 @@ static void haswell_init_clock_gating(struct drm_device *dev)
>
>         ilk_init_lp_watermarks(dev);
>
> -       /* WaApplyL3ControlAndL3ChickenMode:hsw */
> -       I915_WRITE(GEN7_L3CNTLREG1,
> -                       GEN7_WA_FOR_GEN7_L3_CONTROL);
> -       I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
> -                       GEN7_WA_L3_CHICKEN_MODE);
> -
>         /* L3 caching of data atomics doesn't work -- disable it. */
>         I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
>         I915_WRITE(HSW_ROW_CHICKEN3,
> --
> 1.8.3.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br

[PATCH 20/28] drm/i915: Drop WaDisableRCPBUnitClockGating:vlv

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Only early VLV steppings needed thist. Should no longer be relevant.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 14 +++-----------
 1 file changed, 3 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 0d9ded4..593046a 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4927,24 +4927,16 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
 		   I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
 		   GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
 
-	/* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
-	 * gating disable must be set.  Failure to set it results in
-	 * flickering pixels due to Z write ordering failures after
-	 * some amount of runtime in the Mesa "fire" demo, and Unigine
-	 * Sanctuary and Tropics, and apparently anything else with
-	 * alpha test or pixel discard.
-	 *
+	/*
 	 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
 	 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
 	 *
-	 * Also apply WaDisableVDSUnitClockGating:vlv and
-	 * WaDisableRCPBUnitClockGating:vlv.
+	 * Also apply WaDisableVDSUnitClockGating:vlv.
 	 */
 	I915_WRITE(GEN6_UCGCTL2,
 		   GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
 		   GEN7_TDLUNIT_CLOCK_GATE_DISABLE |
-		   GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
-		   GEN6_RCPBUNIT_CLOCK_GATE_DISABLE);
+		   GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
 
 	/* WaDisableL3Bank2xClockGate:vlv */
 	I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
-- 
1.8.3.2

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Re: [PATCH 20/28] drm/i915: Drop WaDisableRCPBUnitClockGating:vlv

[Rodrigo Vivi]

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>

On Wed, Jan 22, 2014 at 5:32 PM,  <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Only early VLV steppings needed thist. Should no longer be relevant.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 14 +++-----------
>  1 file changed, 3 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 0d9ded4..593046a 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4927,24 +4927,16 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
>                    I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
>                    GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
>
> -       /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
> -        * gating disable must be set.  Failure to set it results in
> -        * flickering pixels due to Z write ordering failures after
> -        * some amount of runtime in the Mesa "fire" demo, and Unigine
> -        * Sanctuary and Tropics, and apparently anything else with
> -        * alpha test or pixel discard.
> -        *
> +       /*
>          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
>          * This implements the WaDisableRCZUnitClockGating:vlv workaround.
>          *
> -        * Also apply WaDisableVDSUnitClockGating:vlv and
> -        * WaDisableRCPBUnitClockGating:vlv.
> +        * Also apply WaDisableVDSUnitClockGating:vlv.
>          */
>         I915_WRITE(GEN6_UCGCTL2,
>                    GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
>                    GEN7_TDLUNIT_CLOCK_GATE_DISABLE |
> -                  GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
> -                  GEN6_RCPBUNIT_CLOCK_GATE_DISABLE);
> +                  GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
>
>         /* WaDisableL3Bank2xClockGate:vlv */
>         I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
> --
> 1.8.3.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br

[PATCH 21/28] drm/i915: Drop WaDisableVDSUtnitClockGating:vlv

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

WaDisableVDSUtnitClockGating was only relevant for early steepings of
VLV.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 593046a..1a45566 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4930,11 +4930,8 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
 	/*
 	 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
 	 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
-	 *
-	 * Also apply WaDisableVDSUnitClockGating:vlv.
 	 */
 	I915_WRITE(GEN6_UCGCTL2,
-		   GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
 		   GEN7_TDLUNIT_CLOCK_GATE_DISABLE |
 		   GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
 
-- 
1.8.3.2

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Re: [PATCH 21/28] drm/i915: Drop WaDisableVDSUtnitClockGating:vlv

[Rodrigo Vivi]

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>

On Wed, Jan 22, 2014 at 5:32 PM,  <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> WaDisableVDSUtnitClockGating was only relevant for early steepings of
> VLV.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 3 ---
>  1 file changed, 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 593046a..1a45566 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4930,11 +4930,8 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
>         /*
>          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
>          * This implements the WaDisableRCZUnitClockGating:vlv workaround.
> -        *
> -        * Also apply WaDisableVDSUnitClockGating:vlv.
>          */
>         I915_WRITE(GEN6_UCGCTL2,
> -                  GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
>                    GEN7_TDLUNIT_CLOCK_GATE_DISABLE |
>                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
>
> --
> 1.8.3.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br

[PATCH 22/28] drm/i915: Drop WaDisableTDLUnitClockGating:vlv

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

WaDisableTDLUnitClockGating is only relevant for early steppings of VLV.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 1a45566..dd68414 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4932,7 +4932,6 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
 	 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
 	 */
 	I915_WRITE(GEN6_UCGCTL2,
-		   GEN7_TDLUNIT_CLOCK_GATE_DISABLE |
 		   GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
 
 	/* WaDisableL3Bank2xClockGate:vlv */
-- 
1.8.3.2

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Re: [PATCH 22/28] drm/i915: Drop WaDisableTDLUnitClockGating:vlv

[Rodrigo Vivi]

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>

On Wed, Jan 22, 2014 at 5:32 PM,  <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> WaDisableTDLUnitClockGating is only relevant for early steppings of VLV.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 1 -
>  1 file changed, 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 1a45566..dd68414 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4932,7 +4932,6 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
>          * This implements the WaDisableRCZUnitClockGating:vlv workaround.
>          */
>         I915_WRITE(GEN6_UCGCTL2,
> -                  GEN7_TDLUNIT_CLOCK_GATE_DISABLE |
>                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
>
>         /* WaDisableL3Bank2xClockGate:vlv */
> --
> 1.8.3.2
>
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br

[PATCH 23/28] drm/i915: gen7_setup_fixed_func_scheduler() actually implements WaVSThreadDispatchOverride

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

The current comments indicate that this function implements
WaVSRefCountFullforceMissDisable, which is only true for HSW.
The original purpose of the function is to implement
WaVSThreadDispatchOverride (and a bit more). Fix up the comments
to match reality.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index dd68414..766bc8a 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4654,11 +4654,18 @@ static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
 {
 	uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
 
+	/*
+	 * WaVSThreadDispatchOverride:ivb,hsw
+	 *
+	 * This actually overrides the dispatch
+	 * mode for all thread types.
+	 */
 	reg &= ~GEN7_FF_SCHED_MASK;
 	reg |= GEN7_FF_TS_SCHED_HW;
 	reg |= GEN7_FF_VS_SCHED_HW;
 	reg |= GEN7_FF_DS_SCHED_HW;
 
+	/* WaVSRefCountFullforceMissDisable:hsw */
 	if (IS_HASWELL(dev_priv->dev))
 		reg &= ~GEN7_FF_VS_REF_CNT_FFME;
 
@@ -4772,7 +4779,6 @@ static void haswell_init_clock_gating(struct drm_device *dev)
 			I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
 			GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
 
-	/* WaVSRefCountFullforceMissDisable:hsw */
 	gen7_setup_fixed_func_scheduler(dev_priv);
 
 	/* WaDisable4x2SubspanOptimization:hsw */
@@ -4852,7 +4858,6 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
 
 	g4x_disable_trickle_feed(dev);
 
-	/* WaVSRefCountFullforceMissDisable:ivb */
 	gen7_setup_fixed_func_scheduler(dev_priv);
 
 	/* WaDisable4x2SubspanOptimization:ivb */
-- 
1.8.3.2

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Re: [PATCH 23/28] drm/i915: gen7_setup_fixed_func_scheduler() actually implements WaVSThreadDispatchOverride

[Rodrigo Vivi]

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>

On Wed, Jan 22, 2014 at 5:32 PM,  <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> The current comments indicate that this function implements
> WaVSRefCountFullforceMissDisable, which is only true for HSW.
> The original purpose of the function is to implement
> WaVSThreadDispatchOverride (and a bit more). Fix up the comments
> to match reality.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 9 +++++++--
>  1 file changed, 7 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index dd68414..766bc8a 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4654,11 +4654,18 @@ static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
>  {
>         uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
>
> +       /*
> +        * WaVSThreadDispatchOverride:ivb,hsw
> +        *
> +        * This actually overrides the dispatch
> +        * mode for all thread types.
> +        */
>         reg &= ~GEN7_FF_SCHED_MASK;
>         reg |= GEN7_FF_TS_SCHED_HW;
>         reg |= GEN7_FF_VS_SCHED_HW;
>         reg |= GEN7_FF_DS_SCHED_HW;
>
> +       /* WaVSRefCountFullforceMissDisable:hsw */
>         if (IS_HASWELL(dev_priv->dev))
>                 reg &= ~GEN7_FF_VS_REF_CNT_FFME;
>
> @@ -4772,7 +4779,6 @@ static void haswell_init_clock_gating(struct drm_device *dev)
>                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
>                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
>
> -       /* WaVSRefCountFullforceMissDisable:hsw */
>         gen7_setup_fixed_func_scheduler(dev_priv);
>
>         /* WaDisable4x2SubspanOptimization:hsw */
> @@ -4852,7 +4858,6 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
>
>         g4x_disable_trickle_feed(dev);
>
> -       /* WaVSRefCountFullforceMissDisable:ivb */
>         gen7_setup_fixed_func_scheduler(dev_priv);
>
>         /* WaDisable4x2SubspanOptimization:ivb */
> --
> 1.8.3.2
>
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br

[PATCH 24/28] drm/i915: Don't apply WaVSThreadDispatchOverride on HSW

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

BSpec states that the thread override values set by
gen7_setup_fixed_func_scheduler() are invalid for HSW. So let's not
muck around with them.

Since gen7_setup_fixed_func_scheduler() now has two totally independent
parts, one for IVB and one for HSW, move the HSW part directly into
haswell_init_clock_gating().

Note tht there's another workaround by the name of
WaHSWVSRefCountFullforceMissDisable which basically claims that later
steppings don't need the fix, but since WaVSRefCountFullforceMissDisable
is listed to be needed for all steppings play it safe and keep applying
the workaround.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 10 ++++------
 1 file changed, 4 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 766bc8a..376a52e 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4655,7 +4655,7 @@ static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
 	uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
 
 	/*
-	 * WaVSThreadDispatchOverride:ivb,hsw
+	 * WaVSThreadDispatchOverride:ivb
 	 *
 	 * This actually overrides the dispatch
 	 * mode for all thread types.
@@ -4665,10 +4665,6 @@ static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
 	reg |= GEN7_FF_VS_SCHED_HW;
 	reg |= GEN7_FF_DS_SCHED_HW;
 
-	/* WaVSRefCountFullforceMissDisable:hsw */
-	if (IS_HASWELL(dev_priv->dev))
-		reg &= ~GEN7_FF_VS_REF_CNT_FFME;
-
 	I915_WRITE(GEN7_FF_THREAD_MODE, reg);
 }
 
@@ -4779,7 +4775,9 @@ static void haswell_init_clock_gating(struct drm_device *dev)
 			I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
 			GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
 
-	gen7_setup_fixed_func_scheduler(dev_priv);
+	/* WaVSRefCountFullforceMissDisable:hsw */
+	I915_WRITE(GEN7_FF_THREAD_MODE,
+		   I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
 
 	/* WaDisable4x2SubspanOptimization:hsw */
 	I915_WRITE(CACHE_MODE_1,
-- 
1.8.3.2

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Re: [PATCH 24/28] drm/i915: Don't apply WaVSThreadDispatchOverride on HSW

[Rodrigo Vivi]

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>

On Wed, Jan 22, 2014 at 5:33 PM,  <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> BSpec states that the thread override values set by
> gen7_setup_fixed_func_scheduler() are invalid for HSW. So let's not
> muck around with them.
>
> Since gen7_setup_fixed_func_scheduler() now has two totally independent
> parts, one for IVB and one for HSW, move the HSW part directly into
> haswell_init_clock_gating().
>
> Note tht there's another workaround by the name of
> WaHSWVSRefCountFullforceMissDisable which basically claims that later
> steppings don't need the fix, but since WaVSRefCountFullforceMissDisable
> is listed to be needed for all steppings play it safe and keep applying
> the workaround.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 10 ++++------
>  1 file changed, 4 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 766bc8a..376a52e 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4655,7 +4655,7 @@ static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
>         uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
>
>         /*
> -        * WaVSThreadDispatchOverride:ivb,hsw
> +        * WaVSThreadDispatchOverride:ivb
>          *
>          * This actually overrides the dispatch
>          * mode for all thread types.
> @@ -4665,10 +4665,6 @@ static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
>         reg |= GEN7_FF_VS_SCHED_HW;
>         reg |= GEN7_FF_DS_SCHED_HW;
>
> -       /* WaVSRefCountFullforceMissDisable:hsw */
> -       if (IS_HASWELL(dev_priv->dev))
> -               reg &= ~GEN7_FF_VS_REF_CNT_FFME;
> -
>         I915_WRITE(GEN7_FF_THREAD_MODE, reg);
>  }
>
> @@ -4779,7 +4775,9 @@ static void haswell_init_clock_gating(struct drm_device *dev)
>                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
>                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
>
> -       gen7_setup_fixed_func_scheduler(dev_priv);
> +       /* WaVSRefCountFullforceMissDisable:hsw */
> +       I915_WRITE(GEN7_FF_THREAD_MODE,
> +                  I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
>
>         /* WaDisable4x2SubspanOptimization:hsw */
>         I915_WRITE(CACHE_MODE_1,
> --
> 1.8.3.2
>
> _______________________________________________
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> http://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br

[PATCH 25/28] drm/i915: VLV wants WaVSThreadDispatchOverride too

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Call gen7_setup_fixed_func_scheduler() on VLV as well.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 376a52e..ff8e72e 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4655,7 +4655,7 @@ static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
 	uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
 
 	/*
-	 * WaVSThreadDispatchOverride:ivb
+	 * WaVSThreadDispatchOverride:ivb,vlv
 	 *
 	 * This actually overrides the dispatch
 	 * mode for all thread types.
@@ -4930,6 +4930,8 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
 		   I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
 		   GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
 
+	gen7_setup_fixed_func_scheduler(dev_priv);
+
 	/*
 	 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
 	 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
-- 
1.8.3.2

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Re: [PATCH 25/28] drm/i915: VLV wants WaVSThreadDispatchOverride too

[Rodrigo Vivi]

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>

On Wed, Jan 22, 2014 at 5:33 PM,  <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Call gen7_setup_fixed_func_scheduler() on VLV as well.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 376a52e..ff8e72e 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4655,7 +4655,7 @@ static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
>         uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
>
>         /*
> -        * WaVSThreadDispatchOverride:ivb
> +        * WaVSThreadDispatchOverride:ivb,vlv
>          *
>          * This actually overrides the dispatch
>          * mode for all thread types.
> @@ -4930,6 +4930,8 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
>                    I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
>                    GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
>
> +       gen7_setup_fixed_func_scheduler(dev_priv);
> +
>         /*
>          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
>          * This implements the WaDisableRCZUnitClockGating:vlv workaround.
> --
> 1.8.3.2
>
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br

[PATCH 26/28] drm/i915: WaDisableDopClockGating isn't applicable to IVB

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

I can't see WaDisableDopClockGating listed for IVB in W/A database.

Also I'm not quite sure we were even disabling the right thing. Register
0x9424 has one DOP clock gating disable bit, amd 0xe4f4/0xf4f4 appears
to have  another one, but I don't actually know which is the one were
suposed to frob. This question is more relevant for VLV where this
workaround is still being applied via register 0xe4f4. Maybe it should
actually use 0x9424 instead.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 12 ------------
 1 file changed, 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index ff8e72e..d95a3a6 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4826,18 +4826,6 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
 	I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
 		   GEN7_WA_L3_CHICKEN_MODE);
 
-	/* WaDisableDopClockGating:ivb */
-	if (IS_IVB_GT1(dev))
-		I915_WRITE(GEN7_ROW_CHICKEN2,
-			   _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
-	else {
-		/* must write both registers */
-		I915_WRITE(GEN7_ROW_CHICKEN2,
-			   _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
-		I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
-			   _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
-	}
-
 	/* WaForceL3Serialization:ivb */
 	I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
 		   ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
-- 
1.8.3.2

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Re: [PATCH 26/28] drm/i915: WaDisableDopClockGating isn't applicable to IVB

[Rodrigo Vivi]

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>

On Wed, Jan 22, 2014 at 5:33 PM,  <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> I can't see WaDisableDopClockGating listed for IVB in W/A database.
>
> Also I'm not quite sure we were even disabling the right thing. Register
> 0x9424 has one DOP clock gating disable bit, amd 0xe4f4/0xf4f4 appears
> to have  another one, but I don't actually know which is the one were
> suposed to frob. This question is more relevant for VLV where this
> workaround is still being applied via register 0xe4f4. Maybe it should
> actually use 0x9424 instead.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 12 ------------
>  1 file changed, 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index ff8e72e..d95a3a6 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4826,18 +4826,6 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
>         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
>                    GEN7_WA_L3_CHICKEN_MODE);
>
> -       /* WaDisableDopClockGating:ivb */
> -       if (IS_IVB_GT1(dev))
> -               I915_WRITE(GEN7_ROW_CHICKEN2,
> -                          _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
> -       else {
> -               /* must write both registers */
> -               I915_WRITE(GEN7_ROW_CHICKEN2,
> -                          _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
> -               I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
> -                          _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
> -       }
> -
>         /* WaForceL3Serialization:ivb */
>         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
>                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
> --
> 1.8.3.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br

[PATCH 27/28] drm/i915: Clarify WaDisable4x2SubspanOptimization situation for VLV

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

WaDisable4x2SubspanOptimization isn't listed for VLV in the workaround
database, but BSpec says that the relevant bit must be set. Add a
comment to remind people of this.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index d95a3a6..ca87ea9 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4932,6 +4932,10 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
 
 	I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
 
+	/*
+	 * BSpec says this must be set, even though
+	 * WaDisable4x2SubspanOptimization isn't listed for VLV.
+	 */
 	I915_WRITE(CACHE_MODE_1,
 		   _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
 
-- 
1.8.3.2

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Re: [PATCH 27/28] drm/i915: Clarify WaDisable4x2SubspanOptimization situation for VLV

[Rodrigo Vivi]

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>

On Wed, Jan 22, 2014 at 5:33 PM,  <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> WaDisable4x2SubspanOptimization isn't listed for VLV in the workaround
> database, but BSpec says that the relevant bit must be set. Add a
> comment to remind people of this.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 4 ++++
>  1 file changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index d95a3a6..ca87ea9 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4932,6 +4932,10 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
>
>         I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
>
> +       /*
> +        * BSpec says this must be set, even though
> +        * WaDisable4x2SubspanOptimization isn't listed for VLV.
> +        */
>         I915_WRITE(CACHE_MODE_1,
>                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
>
> --
> 1.8.3.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br

[PATCH 28/28] Revert "drm/i915: set conservative clock gating values on VLV v2"

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

We're disabling a boatload of clock gating features on VLV. Maybe these
days we don't need to do that. At least I'm not aware of any workarounds
with this level of paranoia.

This reverts commit 4e8c84a5b14bbb5b88c63941f1d939560f4abd0b.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 11 +----------
 1 file changed, 1 insertion(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index ca87ea9..1518a9b 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4950,16 +4950,7 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
 	 * Disable clock gating on th GCFG unit to prevent a delay
 	 * in the reporting of vblank events.
 	 */
-	I915_WRITE(VLV_GUNIT_CLOCK_GATE, 0xffffffff);
-
-	/* Conservative clock gating settings for now */
-	I915_WRITE(0x9400, 0xffffffff);
-	I915_WRITE(0x9404, 0xffffffff);
-	I915_WRITE(0x9408, 0xffffffff);
-	I915_WRITE(0x940c, 0xffffffff);
-	I915_WRITE(0x9410, 0xffffffff);
-	I915_WRITE(0x9414, 0xffffffff);
-	I915_WRITE(0x9418, 0xffffffff);
+	I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
 }
 
 static void g4x_init_clock_gating(struct drm_device *dev)
-- 
1.8.3.2

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Re: [PATCH 28/28] Revert "drm/i915: set conservative clock gating values on VLV v2"

[Rodrigo Vivi]

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>

On Wed, Jan 22, 2014 at 5:33 PM,  <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> We're disabling a boatload of clock gating features on VLV. Maybe these
> days we don't need to do that. At least I'm not aware of any workarounds
> with this level of paranoia.
>
> This reverts commit 4e8c84a5b14bbb5b88c63941f1d939560f4abd0b.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 11 +----------
>  1 file changed, 1 insertion(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index ca87ea9..1518a9b 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4950,16 +4950,7 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
>          * Disable clock gating on th GCFG unit to prevent a delay
>          * in the reporting of vblank events.
>          */
> -       I915_WRITE(VLV_GUNIT_CLOCK_GATE, 0xffffffff);
> -
> -       /* Conservative clock gating settings for now */
> -       I915_WRITE(0x9400, 0xffffffff);
> -       I915_WRITE(0x9404, 0xffffffff);
> -       I915_WRITE(0x9408, 0xffffffff);
> -       I915_WRITE(0x940c, 0xffffffff);
> -       I915_WRITE(0x9410, 0xffffffff);
> -       I915_WRITE(0x9414, 0xffffffff);
> -       I915_WRITE(0x9418, 0xffffffff);
> +       I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
>  }
>
>  static void g4x_init_clock_gating(struct drm_device *dev)
> --
> 1.8.3.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br

Re: [PATCH 28/28] Revert "drm/i915: set conservative clock gating values on VLV v2"

[Daniel Vetter]

On Wed, Jan 29, 2014 at 11:11:57AM -0200, Rodrigo Vivi wrote:
> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>

Ok, I've pulled in the last batch of reviewed patches into dinq. But I'm
not sure whether I haven't missed anything or whether there's still an
earlier patch that needs review or rework. So please yell ;-)

Thanks, Daniel
> 
> On Wed, Jan 22, 2014 at 5:33 PM,  <ville.syrjala@linux.intel.com> wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > We're disabling a boatload of clock gating features on VLV. Maybe these
> > days we don't need to do that. At least I'm not aware of any workarounds
> > with this level of paranoia.
> >
> > This reverts commit 4e8c84a5b14bbb5b88c63941f1d939560f4abd0b.
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_pm.c | 11 +----------
> >  1 file changed, 1 insertion(+), 10 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index ca87ea9..1518a9b 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -4950,16 +4950,7 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
> >          * Disable clock gating on th GCFG unit to prevent a delay
> >          * in the reporting of vblank events.
> >          */
> > -       I915_WRITE(VLV_GUNIT_CLOCK_GATE, 0xffffffff);
> > -
> > -       /* Conservative clock gating settings for now */
> > -       I915_WRITE(0x9400, 0xffffffff);
> > -       I915_WRITE(0x9404, 0xffffffff);
> > -       I915_WRITE(0x9408, 0xffffffff);
> > -       I915_WRITE(0x940c, 0xffffffff);
> > -       I915_WRITE(0x9410, 0xffffffff);
> > -       I915_WRITE(0x9414, 0xffffffff);
> > -       I915_WRITE(0x9418, 0xffffffff);
> > +       I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
> >  }
> >
> >  static void g4x_init_clock_gating(struct drm_device *dev)
> > --
> > 1.8.3.2
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> 
> 
> -- 
> Rodrigo Vivi
> Blog: http://blog.vivi.eng.br
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
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-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch