From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [PATCH] drm/i915: vlv: fix DP PHY lockup due to invalid PP sequencer setup Date: Thu, 30 Jan 2014 16:52:24 +0100 Message-ID: <20140130155224.GU17001@phenom.ffwll.local> References: <1391093442-16520-1-git-send-email-imre.deak@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mail-la0-f46.google.com (mail-la0-f46.google.com [209.85.215.46]) by gabe.freedesktop.org (Postfix) with ESMTP id 3F4CB11F2B4 for ; Thu, 30 Jan 2014 07:52:29 -0800 (PST) Received: by mail-la0-f46.google.com with SMTP id b8so2716825lan.33 for ; Thu, 30 Jan 2014 07:52:28 -0800 (PST) Content-Disposition: inline In-Reply-To: <1391093442-16520-1-git-send-email-imre.deak@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org To: Imre Deak Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Thu, Jan 30, 2014 at 04:50:42PM +0200, Imre Deak wrote: > Atm we setup the HW panel power sequencer logic both for eDP and DP > ports. On eDP we then go on and start the power on sequence and commence > with link training when it's ready. On DP we don't do the power on > sequencing but do the link training immediately. At this point the DP > PHY block gets stuck, since - supposedly - it is waiting for the power > on sequence to finish. The actual register write that seems to hold off > the PHY is PIPEX_PP_ON_DELAYS[Panel Control Port Select]. Writing here > a non-0 value eventually sets PIPEX_PP_STATUS[Require Asset Status] to > 1 and blocks the PHY until the panel power on is ready. > = > Fix this by not doing any PP sequencing setup for DP ports. > = > Thanks to Ville Syrj=E4l=E4, Jesse Barnes and Todd Previte for the help in > tracking this down. > = > Signed-off-by: Imre Deak Ah, the infamous ABCD hack we're using all over the place in intel_lvds.c. On edp we didn't have a need for it thus far since the "require asset status" checks have all been fused of, with the PP being on the PCH and the edp port on the north display block. If this is really all we need to appease the hardware then I'm heavily in favour of it as opposed to resurrect the ABCD hack for intel_dp.c. One thing though: Should we add a check for the "Required Asset Status" bit somewhere? I don't really have a good idea for a spot to put this into, hence the question. -Daniel > --- > drivers/gpu/drm/i915/intel_dp.c | 10 ++++++---- > 1 file changed, 6 insertions(+), 4 deletions(-) > = > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel= _dp.c > index ffac7e8..b744073 100644 > --- a/drivers/gpu/drm/i915/intel_dp.c > +++ b/drivers/gpu/drm/i915/intel_dp.c > @@ -1933,10 +1933,12 @@ static void vlv_pre_enable_dp(struct intel_encode= r *encoder) > = > mutex_unlock(&dev_priv->dpio_lock); > = > - /* init power sequencer on this pipe and port */ > - intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq); > - intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, > - &power_seq); > + if (is_edp(intel_dp)) { > + /* init power sequencer on this pipe and port */ > + intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq); > + intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, > + &power_seq); > + } > = > intel_enable_dp(encoder); > = > -- = > 1.8.4 > = > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- = Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch