From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH 08/28] drm/i915: Fix IVB GT2 WaDisableDopClockGating and WaDisablePSDDualDispatchEnable Date: Fri, 31 Jan 2014 11:28:12 +0200 Message-ID: <20140131092812.GV9454@intel.com> References: <1390419184-4450-1-git-send-email-ville.syrjala@linux.intel.com> <1390419184-4450-9-git-send-email-ville.syrjala@linux.intel.com> <20140124175845.GL9454@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTP id 36EFC87424 for ; Fri, 31 Jan 2014 01:28:36 -0800 (PST) Content-Disposition: inline In-Reply-To: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org To: Rodrigo Vivi Cc: intel-gfx List-Id: intel-gfx@lists.freedesktop.org On Tue, Jan 28, 2014 at 10:06:05AM -0200, Rodrigo Vivi wrote: > I agree that spec is strange, but following the spec correctly result > for this and next patch would be only this: > = > if (IS_IVB_GT1(dev)) > I915_WRITE(GEN7_HALF_SLICE_CHICKEN1, > _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE)); > - else > I915_WRITE(GEN7_HALF_SLICE_CHICKEN1_GT2, > _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE)); > } That would match what the w/a database says. But bspec says otherwise. But anyway Chris confirmed on his GT1 that GEN7_HALF_SLICE_CHICKEN1_GT2 doesn't exist there, so I think these patches are correct. > = > On Fri, Jan 24, 2014 at 3:58 PM, Ville Syrj=E4l=E4 > wrote: > > On Fri, Jan 24, 2014 at 03:32:08PM -0200, Rodrigo Vivi wrote: > >> Your patch itself makes sense, but the registers values there are at i= 915_reg.h > >> differs from what I see at BSpec: > >> > >> #define GEN7_ROW_CHICKEN2 0xe4f4 > >> #define GEN7_ROW_CHICKEN2_GT2 0xf4f4 > >> > >> against > >> Address: 0E4F0h > >> Valid Projects: [DevIVB, EXCLUDE(DevIVB:GT2)] > >> Address: 0F4F0h > >> Valid Projects: [DevIVB:GT2] > > > > ROW_CHICKEN vs. ROW_CHICKEN2 > > > >> > >> Also, I couldn't see the wa description at wa_database... > >> description was empty for me.. > > > > Which one? WaDisableDopClockGating? It's not in the list for IVB, > > so in order to see it you need to pick another platform which > > includes this w/a. > > > >> > >> On Wed, Jan 22, 2014 at 5:32 PM, wrot= e: > >> > From: Ville Syrj=E4l=E4 > >> > > >> > IVB GT2 has two registers for these things, and both must be written. > >> > > >> > To add a bit more confusion both Bspec and the W/A database state th= at > >> > WaDisablePSDDualDispatchEnable is only needed for IVB GT1, but the W= /A > >> > database also says to write even the second GT2 only register. So I > >> > don't really know what the right thing here is. > >> > > >> > Signed-off-by: Ville Syrj=E4l=E4 > >> > --- > >> > drivers/gpu/drm/i915/intel_pm.c | 13 ++++++++++--- > >> > 1 file changed, 10 insertions(+), 3 deletions(-) > >> > > >> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/= intel_pm.c > >> > index 6a1d98a..b268a55 100644 > >> > --- a/drivers/gpu/drm/i915/intel_pm.c > >> > +++ b/drivers/gpu/drm/i915/intel_pm.c > >> > @@ -4828,9 +4828,13 @@ static void ivybridge_init_clock_gating(struc= t drm_device *dev) > >> > if (IS_IVB_GT1(dev)) > >> > I915_WRITE(GEN7_HALF_SLICE_CHICKEN1, > >> > _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_D= ISPATCH_ENABLE)); > >> > - else > >> > + else { > >> > + /* must write both registers */ > >> > + I915_WRITE(GEN7_HALF_SLICE_CHICKEN1, > >> > + _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_D= ISPATCH_ENABLE)); > >> > I915_WRITE(GEN7_HALF_SLICE_CHICKEN1_GT2, > >> > _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_D= ISPATCH_ENABLE)); > >> > + } > >> > > >> > /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb work= around. */ > >> > I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1, > >> > @@ -4846,10 +4850,13 @@ static void ivybridge_init_clock_gating(stru= ct drm_device *dev) > >> > if (IS_IVB_GT1(dev)) > >> > I915_WRITE(GEN7_ROW_CHICKEN2, > >> > _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISAB= LE)); > >> > - else > >> > + else { > >> > + /* must write both registers */ > >> > + I915_WRITE(GEN7_ROW_CHICKEN2, > >> > + _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISAB= LE)); > >> > I915_WRITE(GEN7_ROW_CHICKEN2_GT2, > >> > _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISAB= LE)); > >> > - > >> > + } > >> > > >> > /* WaForceL3Serialization:ivb */ > >> > I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) & > >> > -- > >> > 1.8.3.2 > >> > > >> > _______________________________________________ > >> > Intel-gfx mailing list > >> > Intel-gfx@lists.freedesktop.org > >> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx > >> > >> > >> > >> -- > >> Rodrigo Vivi > >> Blog: http://blog.vivi.eng.br > > > > -- > > Ville Syrj=E4l=E4 > > Intel OTC > = > = > = > -- = > Rodrigo Vivi > Blog: http://blog.vivi.eng.br -- = Ville Syrj=E4l=E4 Intel OTC