From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH v6] drm/i915/vlv: WA to fix Voltage not getting dropped to Vmin when Gfx is power gated. Date: Fri, 31 Jan 2014 19:10:59 +0200 Message-ID: <20140131171059.GY9454@intel.com> References: <1391103496-27418-1-git-send-email-deepak.s@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga14.intel.com (mga14.intel.com [143.182.124.37]) by gabe.freedesktop.org (Postfix) with ESMTP id 864E0FA3DA for ; Fri, 31 Jan 2014 09:11:06 -0800 (PST) Content-Disposition: inline In-Reply-To: <1391103496-27418-1-git-send-email-deepak.s@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org To: deepak.s@intel.com Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Thu, Jan 30, 2014 at 11:08:16PM +0530, deepak.s@intel.com wrote: > From: Deepak S > = > When we enter RC6 and GFX Clocks are off, the voltage remains higher > than Vmin. When we try to set the freq to RPn, it might fail since the > Gfx clocks are down. So to fix this in Gfx idle, Bring the GFX clock up > and set the freq to RPn then move GFx down. > = > v2: remove vlv_update_rps_cur_delay function. Update commit message (Dani= el) > = > v3: Fix the timeout during wait for gfx clock (Jesse) > = > v4: addressed comments on set freq and punit wait (Ville) > = > v5: use wait_for while waiting for GFX clk to be up. (Daniel) > update cur_delay before requesting min_delay. (Ville) > = > v6: use wait_for while waiting for punit. (Ville) > = > Signed-off-by: Deepak S > Reviewed-by: Ville Syrj=E4 ^^ Stuff missing from my name. -- = Ville Syrj=E4l=E4 Intel OTC