From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH v7] drm/i915: Reorganize display pipe register accesses Date: Tue, 4 Feb 2014 20:20:31 +0200 Message-ID: <20140204182031.GI3891@intel.com> References: <1391516544-2033-1-git-send-email-antti.koskipaa@linux.intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTP id 38990F9F1F for ; Tue, 4 Feb 2014 10:21:25 -0800 (PST) Content-Disposition: inline In-Reply-To: <1391516544-2033-1-git-send-email-antti.koskipaa@linux.intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org To: Antti Koskipaa Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Tue, Feb 04, 2014 at 02:22:24PM +0200, Antti Koskipaa wrote: > RFCv2: Reorganize array indexing so that full offsets can be used as > is. It makes grepping for registers in i915_reg.h much easier. Also > move offset arrays to intel_device_info. > = > v1: Fixed offsets for VLV, proper eDP handling > = > v2: Fixed BCLRPAT, PIPESRC, PIPECONF and DSP* macros. > = > v3: Added EDP pipe comment, removed redundant offset arrays for > MSA_MISC and DDI_FUNC_CTL. > = > v4: Rename patch and report object size increase. > = > v5: Change location of commas, add PIPE_EDP into enum pipe > = > v6: Insert PIPE_EDP_OFFSET into pipe offset array > = > v7: Set I915_MAX_PIPES back to 3, change more registers accessors > to use the new macros, get rid of _PIPE_INC and add dev_priv > as a parameter where required by the new macros. > = > Upcoming hardware will not have the various display pipe register > ranges evenly spaced in memory. Change register address calculations > into array lookups. > = > Tested on SNB, VLV, IVB, Gen2 and HSW w/eDP. > = > I left the UMS cruft untouched. > = > Size differences: > text data bss dec hex filename > 596431 4634 56 601121 92c21 i915.ko (new) > 593199 4634 56 597889 91f81 i915.ko (old) > = > Signed-off-by: Antti Koskipaa Reviewed-by: Ville Syrj=E4l=E4 Tested-by: Ville Syrj=E4l=E4 To elaborate a bit, I fired this up on HSW ULT w/ eDP, IVB w/ HDMI, and 855GM w/ LVDS. I think I also tried HSW and IVB with a another HDMI monitor plugged in, and the 855GM w/ VGA plugged in. As added insurance I enabled the reg_rw tracepoint and traced all the register access we do when loading the driver (w/ fbcon enabled to get some modesets in the trace). I compared traces between patched and unpatched kernels and tried to see if there were any significant differences. Couldn't spot anything apart from a few small differences in the order of register accesses due parallel activity. -- = Ville Syrj=E4l=E4 Intel OTC