From mboxrd@z Thu Jan  1 00:00:00 1970
From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= <ville.syrjala@linux.intel.com>
Subject: Re: [PATCH 1/7] drm/i915: Fix SNB GT_MODE register setup
Date: Wed, 5 Feb 2014 11:27:31 +0200
Message-ID: <20140205092731.GJ3891@intel.com>
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To: Chris Wilson <chris@chris-wilson.co.uk>, intel-gfx@lists.freedesktop.org
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On Tue, Feb 04, 2014 at 09:23:06PM +0000, Chris Wilson wrote:
> On Tue, Feb 04, 2014 at 09:59:15PM +0200, ville.syrjala@linux.intel.com w=
rote:
> > From: Ville Syrj=E4l=E4 <ville.syrjala@linux.intel.com>
> > =

> > On SNB we set up WaSetupGtModeTdRowDispatch:snb early in
> > gen6_init_clock_gating(). That sets a bit in the GEN6_GT_MODE register.
> > However later we go and disable all the bits in the same register. And
> > then we go on to set some other bit. So apparently we never actually
> > implemented this workaround since the "disable all bits" part was there
> > already before the w/a got supposedly implemented.
> > =

> > These are the relevant commits:
> > =

> >  commit 6547fbdbfff62c99e4f7b4f985ff8b3454f33b0f
> >  Author: Daniel Vetter <daniel.vetter@ffwll.ch>
> >  Date:   Fri Dec 14 23:38:29 2012 +0100
> > =

> >     drm/i915: Implement WaSetupGtModeTdRowDispatch
> > =

> >  commit f8f2ac9a76b0f80a6763ca316116a7bab8486997
> >  Author: Ben Widawsky <ben@bwidawsk.net>
> >  Date:   Wed Oct 3 19:34:24 2012 -0700
> > =

> >     drm/i915: Fix GT_MODE default value
> > =

> > So, let's drop the "disable all bits" part, move both writes to
> > closer proxomity to each other, and name the WIZ hashing bits
> > appropriately. BSpec is still a bit confused how the bits should
> > actually be interpreted, but I took the the description for the
> > high bit since the low bit part only lists values for a single bit.
> > =

> > Also add a comment about our choice of WIZ hashing mode.
> =

> Changing WiZ hashing mode changes the valid number of threads and
> userspace assumes best case (WiZ disabled). Worst case we start hanging
> the chip.
> =

> I have no idea how relevant that piece of lore from the spec is, but it
> something to be wary of when making these changes.

The thread numbers seem to depend only on the WIZ hashing disable bit.
I'm not touching that one.

-- =

Ville Syrj=E4l=E4
Intel OTC