From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH v2 3/3] drm/i915/vlv: Modified the programming of 2 regs in Ring initialisation Date: Fri, 7 Feb 2014 16:44:10 +0200 Message-ID: <20140207144410.GW3891@intel.com> References: <1391775732-7431-1-git-send-email-akash.goel@intel.com> <1391775732-7431-4-git-send-email-akash.goel@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTP id 85C48FBAA1 for ; Fri, 7 Feb 2014 06:44:15 -0800 (PST) Content-Disposition: inline In-Reply-To: <1391775732-7431-4-git-send-email-akash.goel@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org To: akash.goel@intel.com Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Fri, Feb 07, 2014 at 05:52:12PM +0530, akash.goel@intel.com wrote: > From: Akash Goel > = > Modified programming of following 2 regs in Render ring initialisation fn. > 1. GFX_MODE_GEN7 (Enabling TLB invalidate) > 2. MI_MODE (Enabling MI Flush) > = > v2: Removed the enabling of MI_FLUSH (Ville) > Added new comments (Ville). > = > Signed-off-by: Akash Goel > --- > drivers/gpu/drm/i915/intel_ringbuffer.c | 19 ++++++++++++++----- > 1 file changed, 14 insertions(+), 5 deletions(-) > = > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i9= 15/intel_ringbuffer.c > index 49370a1..0d7d927b 100644 > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c > @@ -563,7 +563,10 @@ static int init_render_ring(struct intel_ring_buffer= *ring) > int ret =3D init_ring_common(ring); > = > if (INTEL_INFO(dev)->gen > 3) > - I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH)); > + /* FIXME, should also apply to ivb */ > + if (!IS_VALLEYVIEW(dev)) > + I915_WRITE(MI_MODE, > + _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH)); Was this supposed to be here? I guess it should be a separate patch. > = > /* We need to disable the AsyncFlip performance optimisations in order > * to use MI_WAIT_FOR_EVENT within the CS. It should already be > @@ -579,10 +582,16 @@ static int init_render_ring(struct intel_ring_buffe= r *ring) > I915_WRITE(GFX_MODE, > _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_ALWAYS)); > = > - if (IS_GEN7(dev)) > - I915_WRITE(GFX_MODE_GEN7, > - _MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) | > - _MASKED_BIT_ENABLE(GFX_REPLAY_MODE)); > + if (IS_GEN7(dev)) { > + if (IS_VALLEYVIEW(dev)) { > + /* FIXME, should also apply to ivb */ > + I915_WRITE(GFX_MODE_GEN7, > + _MASKED_BIT_ENABLE(GFX_REPLAY_MODE)); > + } else > + I915_WRITE(GFX_MODE_GEN7, > + _MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) | > + _MASKED_BIT_ENABLE(GFX_REPLAY_MODE)); > + } > = > if (INTEL_INFO(dev)->gen >=3D 5) { > ret =3D init_pipe_control(ring); > -- = > 1.8.5.2 > = > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- = Ville Syrj=E4l=E4 Intel OTC