From: Daniel Vetter <daniel@ffwll.ch>
To: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
Cc: Intel Graphics <intel-gfx@lists.freedesktop.org>
Subject: Re: [PATCH] drm/i915: Fix correct FIFO size for Baytrail
Date: Fri, 7 Feb 2014 19:58:47 +0100 [thread overview]
Message-ID: <20140207185847.GE17001@phenom.ffwll.local> (raw)
In-Reply-To: <20140207155816.GY3891@intel.com>
On Fri, Feb 07, 2014 at 05:58:16PM +0200, Ville Syrjälä wrote:
> On Fri, Feb 07, 2014 at 08:43:12PM +0530, Vijay Purushothaman wrote:
> > B-spec says the FIFO total size is 512. So fix this to 512.
> >
> > Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_reg.h | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index cc3ea04..fb73031 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -3395,7 +3395,7 @@
> > #define I915_FIFO_LINE_SIZE 64
> > #define I830_FIFO_LINE_SIZE 32
> >
> > -#define VALLEYVIEW_FIFO_SIZE 255
> > +#define VALLEYVIEW_FIFO_SIZE 511
> > #define G4X_FIFO_SIZE 127
> > #define I965_FIFO_SIZE 512
> > #define I945_FIFO_SIZE 127
>
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Queued for -next, thanks for the patch.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
next prev parent reply other threads:[~2014-02-07 18:58 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-02-07 15:13 [PATCH] drm/i915: Fix correct FIFO size for Baytrail Vijay Purushothaman
2014-02-07 15:58 ` Ville Syrjälä
2014-02-07 16:26 ` Vijay Purushothaman
2014-02-07 19:38 ` Ville Syrjälä
2014-02-07 18:58 ` Daniel Vetter [this message]
2014-02-12 17:24 ` Imre Deak
2014-02-12 17:27 ` Imre Deak
2014-02-12 17:53 ` Daniel Vetter
2014-02-13 15:46 ` Purushothaman, Vijay A
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