From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH 4/7] drm/i915: Disable SF pipelined attribute fetch for SNB Date: Sat, 8 Feb 2014 21:57:55 +0200 Message-ID: <20140208195755.GE3891@intel.com> References: <1391543961-1553-1-git-send-email-ville.syrjala@linux.intel.com> <1391543961-1553-5-git-send-email-ville.syrjala@linux.intel.com> <52F53EB7.9020001@whitecape.org> <20140208172803.GG17001@phenom.ffwll.local> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTP id A6DA6FA47D for ; Sat, 8 Feb 2014 11:57:59 -0800 (PST) Content-Disposition: inline In-Reply-To: <20140208172803.GG17001@phenom.ffwll.local> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org To: Daniel Vetter Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Sat, Feb 08, 2014 at 06:28:03PM +0100, Daniel Vetter wrote: > On Fri, Feb 07, 2014 at 12:14:47PM -0800, Kenneth Graunke wrote: > > On 02/04/2014 11:59 AM, ville.syrjala@linux.intel.com wrote: > > > From: Ville Syrj=E4l=E4 > > > = > > > According to Bspec we need to disable SF pipelined attribute fetch > > > whenever SF outputs exceed 16 and normal clip mode is used. A quick > > > glance at Mesa suggests that these conditions could happen. So let's > > > just always set the magic bit. > > > = > > > Signed-off-by: Ville Syrj=E4l=E4 > > > --- > > > drivers/gpu/drm/i915/i915_reg.h | 3 ++- > > > drivers/gpu/drm/i915/intel_pm.c | 8 ++++++++ > > > 2 files changed, 10 insertions(+), 1 deletion(-) > > > = > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i= 915_reg.h > > > index 7aa2cf5..0334507 100644 > > > --- a/drivers/gpu/drm/i915/i915_reg.h > > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > > @@ -790,7 +790,8 @@ > > > #define _3D_CHICKEN3 0x02090 > > > #define _3D_CHICKEN_SF_DISABLE_OBJEND_CULL (1 << 10) > > > #define _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL (1 << 5) > > > -#define _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(x) ((x)<<1) > > > +#define _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(x) ((x)<<1) /* gen8+ = */ > > > +#define _3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH (1 << 1) /* ge= n6 */ > > > = > > > #define MI_MODE 0x0209c > > > # define VS_TIMER_DISPATCH (1 << 6) > > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/i= ntel_pm.c > > > index 6a09281..7247084 100644 > > > --- a/drivers/gpu/drm/i915/intel_pm.c > > > +++ b/drivers/gpu/drm/i915/intel_pm.c > > > @@ -4683,6 +4683,14 @@ static void gen6_init_clock_gating(struct drm_= device *dev) > > > _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL)); > > > = > > > /* > > > + * Bspec says: > > > + * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal= and > > > + * 3DSTATE_SF number of SF output attributes is more than 16." > > > + */ > > > + I915_WRITE(_3D_CHICKEN3, > > > + _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH= )); > > > + > > > + /* > > > * According to the spec the following bits should be > > > * set in order to enable memory self-refresh and fbc: > > > * The bit21 and bit22 of 0x42000 > > > = > > = > > I'm almost positive Mesa will hit this case. Nice catch! > > = > > Reviewed-by: Kenneth Graunke > = > Queued for -next, thanks for the patch. Any chance that this would apply > to one of our leftover snb gpu hang issues? Unfortunately BSpec doesn't say what might happen if we don't set the bit, nor did I find anything relevant in the w/a database. -- = Ville Syrj=E4l=E4 Intel OTC