From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [PATCH 5/8] drm/i915: Disable display when fused off Date: Mon, 10 Feb 2014 10:12:02 +0100 Message-ID: <20140210091202.GM17001@phenom.ffwll.local> References: <1391800374-24904-1-git-send-email-damien.lespiau@intel.com> <1391800374-24904-6-git-send-email-damien.lespiau@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mail-ea0-f176.google.com (mail-ea0-f176.google.com [209.85.215.176]) by gabe.freedesktop.org (Postfix) with ESMTP id 39C74FA6B8 for ; Mon, 10 Feb 2014 01:12:07 -0800 (PST) Received: by mail-ea0-f176.google.com with SMTP id h14so2817904eaj.35 for ; Mon, 10 Feb 2014 01:12:06 -0800 (PST) Content-Disposition: inline In-Reply-To: <1391800374-24904-6-git-send-email-damien.lespiau@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org To: Damien Lespiau Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Fri, Feb 07, 2014 at 07:12:51PM +0000, Damien Lespiau wrote: > FUSE_STRAP has a bit to inform us that the display has been fused off. > Use it to setup the definitive number of pipes at run-time. > = > v2: actually tweak num_pipes, not num_planes > v3: also tests SFUSE_STRAP bit 7 > v4: rebase on top of drm-nightly > use DRM_INFO() for the message telling display is fused off > try to read the FUSE_LOCK bit to determine if PCH display is disabled > = > Reviewed-by: Mika Kuoppala (for v3) > Reviewed-by: Ville Syrj=E4l=E4 (for v3) > Signed-off-by: Damien Lespiau > --- > drivers/gpu/drm/i915/i915_dma.c | 31 ++++++++++++++++++++++++++++++- > drivers/gpu/drm/i915/i915_reg.h | 2 ++ > 2 files changed, 32 insertions(+), 1 deletion(-) > = > diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_= dma.c > index e281298..283ace8 100644 > --- a/drivers/gpu/drm/i915/i915_dma.c > +++ b/drivers/gpu/drm/i915/i915_dma.c > @@ -1466,16 +1466,45 @@ static void i915_dump_device_info(struct drm_i915= _private *dev_priv) > * - it's judged too laborious to fill n static structures with the li= mit > * when a simple if statement does the job, > * - run-time checks (eg read fuse/strap registers) are needed. > + * > + * This function needs to be called: > + * - after the MMIO has been setup as we are reading registers, > + * - after the PCH has been detected, > + * - before the first usage of the fields it can tweak. > */ > static void intel_device_info_runtime_init(struct drm_device *dev) > { > + struct drm_i915_private *dev_priv =3D dev->dev_private; > struct intel_device_info *info; > = > - info =3D (struct intel_device_info *)&to_i915(dev)->info; > + info =3D (struct intel_device_info *)&dev_priv->info; > = > info->num_sprites =3D 1; > if (IS_VALLEYVIEW(dev)) > info->num_sprites =3D 2; > + > + if ((INTEL_INFO(dev)->gen =3D=3D 7 || INTEL_INFO(dev)->gen =3D=3D 8) && > + !IS_VALLEYVIEW(dev)) { I think we need a num_pipes > 0 check here, too. Our display hw guy expressed surprise that we didn't hang the machine when reading pch registers on a hsw platform, and Ben learned tha hard way that any such access on ivb hard-hangs the box. Hence I think we need to retain the current code's invariant that we never access the pch registers when num_pipes is 0, like with one of the special pci matching rules. I've merged the preceding patches to dinq meanwhile. -Daniel -- = Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch