From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [PATCH 9/9] drm/i915: PF CRC may not work on HSW Date: Mon, 10 Feb 2014 11:43:50 +0100 Message-ID: <20140210104350.GV17001@phenom.ffwll.local> References: <1391805427-4576-1-git-send-email-rodrigo.vivi@gmail.com> <1391805427-4576-10-git-send-email-rodrigo.vivi@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mail-ea0-f170.google.com (mail-ea0-f170.google.com [209.85.215.170]) by gabe.freedesktop.org (Postfix) with ESMTP id 1BF9EFA189 for ; Mon, 10 Feb 2014 02:43:59 -0800 (PST) Received: by mail-ea0-f170.google.com with SMTP id g15so1112135eak.1 for ; Mon, 10 Feb 2014 02:43:57 -0800 (PST) Content-Disposition: inline In-Reply-To: <1391805427-4576-10-git-send-email-rodrigo.vivi@gmail.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org To: Rodrigo Vivi Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Fri, Feb 07, 2014 at 06:37:07PM -0200, Rodrigo Vivi wrote: > From: Ville Syrj=E4l=E4 > = > When using pipe A and transcoder EDP w/o panel fitter on > HSW, the PF CRC isn't available as the panel fitter is entirely > bypassed. Check for this and refuse to give out CRCs. > = > Signed-off-by: Ville Syrj=E4l=E4 > Signed-off-by: Rodrigo Vivi I've discussed this a bit with Ville and I think the right fix would be to use the DDI A CRC in this case, at least for the auto source, similarly to who we do magic stuff for DP on g4x/vlv. I don't have a suitable hsw machine, only one with desktop edp on DDI E around. So any volunteers? Cheers, Daniel > --- > drivers/gpu/drm/i915/i915_debugfs.c | 29 +++++++++++++++++++++++++++-- > 1 file changed, 27 insertions(+), 2 deletions(-) > = > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i= 915_debugfs.c > index 2dc05c3..de020c0 100644 > --- a/drivers/gpu/drm/i915/i915_debugfs.c > +++ b/drivers/gpu/drm/i915/i915_debugfs.c > @@ -2548,7 +2548,30 @@ static int ilk_pipe_crc_ctl_reg(enum intel_pipe_cr= c_source *source, > return 0; > } > = > -static int ivb_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source, > +static bool hsw_crc_source_pf_ok(struct drm_device *dev, enum pipe pipe) > +{ > + struct drm_i915_private *dev_priv =3D dev->dev_private; > + struct intel_crtc *crtc =3D to_intel_crtc(dev_priv->pipe_to_crtc_mappin= g[pipe]); > + bool ok; > + > + if (!IS_HASWELL(dev) || pipe !=3D PIPE_A) > + return true; > + > + mutex_lock(&crtc->base.mutex); > + > + /* pipe A -> no panel fitter -> transcoder EDP =3D=3D no PF CRC */ > + ok =3D !crtc->active || > + crtc->config.cpu_transcoder !=3D TRANSCODER_EDP || > + crtc->config.pch_pfit.enabled; > + > + mutex_unlock(&crtc->base.mutex); > + > + return ok; > +} > + > +static int ivb_pipe_crc_ctl_reg(struct drm_device *dev, > + enum pipe pipe, > + enum intel_pipe_crc_source *source, > uint32_t *val) > { > if (*source =3D=3D INTEL_PIPE_CRC_SOURCE_AUTO) > @@ -2562,6 +2585,8 @@ static int ivb_pipe_crc_ctl_reg(enum intel_pipe_crc= _source *source, > *val =3D PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB; > break; > case INTEL_PIPE_CRC_SOURCE_PF: > + if (!hsw_crc_source_pf_ok(dev, pipe)) > + return -EINVAL; > *val =3D PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB; > break; > case INTEL_PIPE_CRC_SOURCE_NONE: > @@ -2598,7 +2623,7 @@ static int pipe_crc_set_source(struct drm_device *d= ev, enum pipe pipe, > else if (IS_GEN5(dev) || IS_GEN6(dev)) > ret =3D ilk_pipe_crc_ctl_reg(&source, &val); > else > - ret =3D ivb_pipe_crc_ctl_reg(&source, &val); > + ret =3D ivb_pipe_crc_ctl_reg(dev, pipe, &source, &val); > = > if (ret !=3D 0) > return ret; > -- = > 1.8.3.1 > = > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- = Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch