From mboxrd@z Thu Jan 1 00:00:00 1970 From: Damien Lespiau Subject: Re: [PATCH 8/3] drm/i915: WARN in case we're enabling the pipe and it's enabled Date: Mon, 10 Feb 2014 14:34:18 +0000 Message-ID: <20140210143418.GI9282@strange.amr.corp.intel.com> References: <1389973873-2005-1-git-send-email-przanoni@gmail.com> <1389973873-2005-5-git-send-email-przanoni@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTP id DD86AFA1BD for ; Mon, 10 Feb 2014 06:34:41 -0800 (PST) Content-Disposition: inline In-Reply-To: <1389973873-2005-5-git-send-email-przanoni@gmail.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org To: Paulo Zanoni Cc: intel-gfx@lists.freedesktop.org, Paulo Zanoni List-Id: intel-gfx@lists.freedesktop.org On Fri, Jan 17, 2014 at 01:51:13PM -0200, Paulo Zanoni wrote: > From: Paulo Zanoni > > ... and QUIRK_PIPEA_FORCE is not present. > > I initially thought that case was impossible and just added a WARN on > it, but then I was told this case is possible due to > QUIRK_PIPEA_FORCE. So let's add a WARN that serves two purposes: > - tell us in case we have done something wrong; > - document the only case where we expect this. > > Signed-off-by: Paulo Zanoni Reviewed-by: Damien Lespiau -- Damien > --- > drivers/gpu/drm/i915/intel_display.c | 5 ++++- > 1 file changed, 4 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index 9f356f9..e2df886 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -1791,8 +1791,11 @@ static void intel_enable_pipe(struct intel_crtc *crtc) > > reg = PIPECONF(cpu_transcoder); > val = I915_READ(reg); > - if (val & PIPECONF_ENABLE) > + if (val & PIPECONF_ENABLE) { > + WARN_ON(!(pipe == PIPE_A && > + dev_priv->quirks & QUIRK_PIPEA_FORCE)); > return; > + } > > I915_WRITE(reg, val | PIPECONF_ENABLE); > POSTING_READ(reg); > -- > 1.8.4.2 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx