From mboxrd@z Thu Jan  1 00:00:00 1970
From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= <ville.syrjala@linux.intel.com>
Subject: Re: [PATCH 7/3] drm/i915: remove wait_for_vblank
 argument form intel_enable_pipe
Date: Mon, 10 Feb 2014 16:59:45 +0200
Message-ID: <20140210145945.GQ3891@intel.com>
References: <CA+gsUGQ4Kt+q8xTnqVZRcwSVoAasYTAL3=5JGk5bcFQ7A47JLA@mail.gmail.com>
	<1389973873-2005-1-git-send-email-przanoni@gmail.com>
	<1389973873-2005-4-git-send-email-przanoni@gmail.com>
	<20140210143307.GH9282@strange.amr.corp.intel.com>
Mime-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
Return-path: <intel-gfx-bounces@lists.freedesktop.org>
Received: from mga01.intel.com (mga01.intel.com [192.55.52.88])
	by gabe.freedesktop.org (Postfix) with ESMTP id 4864FFA7A2
	for <intel-gfx@lists.freedesktop.org>;
	Mon, 10 Feb 2014 07:00:08 -0800 (PST)
Content-Disposition: inline
In-Reply-To: <20140210143307.GH9282@strange.amr.corp.intel.com>
List-Unsubscribe: <http://lists.freedesktop.org/mailman/options/intel-gfx>,
	<mailto:intel-gfx-request@lists.freedesktop.org?subject=unsubscribe>
List-Archive: <http://lists.freedesktop.org/archives/intel-gfx>
List-Post: <mailto:intel-gfx@lists.freedesktop.org>
List-Help: <mailto:intel-gfx-request@lists.freedesktop.org?subject=help>
List-Subscribe: <http://lists.freedesktop.org/mailman/listinfo/intel-gfx>,
	<mailto:intel-gfx-request@lists.freedesktop.org?subject=subscribe>
Sender: intel-gfx-bounces@lists.freedesktop.org
Errors-To: intel-gfx-bounces@lists.freedesktop.org
To: Damien Lespiau <damien.lespiau@intel.com>
Cc: intel-gfx@lists.freedesktop.org, Paulo Zanoni <paulo.r.zanoni@intel.com>
List-Id: intel-gfx@lists.freedesktop.org

On Mon, Feb 10, 2014 at 02:33:07PM +0000, Damien Lespiau wrote:
> On Fri, Jan 17, 2014 at 01:51:12PM -0200, Paulo Zanoni wrote:
> > From: Paulo Zanoni <paulo.r.zanoni@intel.com>
> > =

> > Add a nice comment explaining why we shouldn't wait for a vblank on
> > all cases, wait based on the HW gen, and add a comment saying we
> > should probably skip that wait on some of the previous HW gens.
> > =

> > Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> =

> =

> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
> =

> Looking at BSpec for info on this, I didn't find any mention of having
> to wait of a vblank indeed. There's a nice workaround we don't seem to
> implement though (underrun when switching from one to multi-pipes,
> display buffer related). I'm sure that's somewhere in a TODO list :)

We implement something for HSW, but I'm not sure it's quite enough.
In any case I have patches lined up for disabling LP1+ watermarks when
doing one<->many pipes switch for PCH platforms. Which reminds I need
to stop slacking off and get those posted soon.

-- =

Ville Syrj=E4l=E4
Intel OTC