From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH 04/13] drm/i915: Make semaphore updates more precise Date: Tue, 11 Feb 2014 19:13:52 +0200 Message-ID: <20140211171351.GW3891@intel.com> References: <1391025333-31587-1-git-send-email-benjamin.widawsky@intel.com> <1391025333-31587-5-git-send-email-benjamin.widawsky@intel.com> <20140130112542.GI9454@intel.com> <20140211160824.GA10233@bwidawsk.net> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTP id 1F1C4FA67E for ; Tue, 11 Feb 2014 09:14:11 -0800 (PST) Content-Disposition: inline In-Reply-To: <20140211160824.GA10233@bwidawsk.net> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org To: Ben Widawsky Cc: Intel GFX , Ben Widawsky List-Id: intel-gfx@lists.freedesktop.org On Tue, Feb 11, 2014 at 08:08:27AM -0800, Ben Widawsky wrote: > On Thu, Jan 30, 2014 at 01:25:42PM +0200, Ville Syrj=E4l=E4 wrote: > > On Wed, Jan 29, 2014 at 11:55:24AM -0800, Ben Widawsky wrote: > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i9= 15/intel_ringbuffer.c > index 97789ff..3bec0f5 100644 > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c > @@ -635,18 +635,18 @@ static void render_ring_cleanup(struct intel_ring_b= uffer *ring) > static int gen6_signal(struct intel_ring_buffer *signaller, > unsigned int num_dwords) > { > -#define MBOX_UPDATE_DWORDS 4 > +#define MBOX_UPDATE_DWORDS 3 > struct drm_device *dev =3D signaller->dev; > struct drm_i915_private *dev_priv =3D dev->dev_private; > struct intel_ring_buffer *useless; > int i, ret, num_rings; > = > num_rings =3D hweight_long(INTEL_INFO(dev)->ring_mask); > - num_dwords =3D round_up((num_rings-1) * MBOX_UPDATE_DWORDS, 2); > + num_dwords +=3D round_up((num_rings-1) * MBOX_UPDATE_DWORDS, 2); > #undef MBOX_UPDATE_DWORDS > = > /* XXX: + 4 for the caller */ > - ret =3D intel_ring_begin(signaller, num_dwords + 4); > + ret =3D intel_ring_begin(signaller, num_dwords); > if (ret) > return ret; > = > @@ -656,7 +656,6 @@ static int gen6_signal(struct intel_ring_buffer *sign= aller, > intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1)); > intel_ring_emit(signaller, mbox_reg); > intel_ring_emit(signaller, signaller->outstanding_lazy_seqno); > - intel_ring_emit(signaller, MI_NOOP); > } > } Still need to emit an extra MI_NOOP if num_dwords got rounded. > = > @@ -1877,9 +1876,10 @@ int intel_init_render_ring_buffer(struct drm_devic= e *dev) > ring->irq_enable_mask =3D GT_RENDER_USER_INTERRUPT; > ring->get_seqno =3D gen6_ring_get_seqno; > ring->set_seqno =3D ring_set_seqno; > - ring->semaphore.sync_to =3D gen6_ring_sync; > - if (i915_semaphore_is_enabled(dev)) > + if (i915_semaphore_is_enabled(dev)) { > + ring->semaphore.sync_to =3D gen6_ring_sync; > ring->semaphore.signal =3D gen6_signal; > + } > ring->semaphore.mbox[RCS] =3D MI_SEMAPHORE_SYNC_INVALID; > ring->semaphore.mbox[VCS] =3D MI_SEMAPHORE_SYNC_RV; > ring->semaphore.mbox[BCS] =3D MI_SEMAPHORE_SYNC_RB; -- = Ville Syrj=E4l=E4 Intel OTC