From mboxrd@z Thu Jan  1 00:00:00 1970
From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= <ville.syrjala@linux.intel.com>
Subject: Re: [PATCH] drm/i915: Avoid div by zero when pixel
 clock is large
Date: Fri, 14 Feb 2014 14:40:39 +0200
Message-ID: <20140214124039.GI3852@intel.com>
References: <1392380337-11462-1-git-send-email-ville.syrjala@linux.intel.com>
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To: Chris Wilson <chris@chris-wilson.co.uk>, intel-gfx@lists.freedesktop.org
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On Fri, Feb 14, 2014 at 12:28:29PM +0000, Chris Wilson wrote:
> On Fri, Feb 14, 2014 at 02:18:57PM +0200, ville.syrjala@linux.intel.com w=
rote:
> > From: Ville Syrj=E4l=E4 <ville.syrjala@linux.intel.com>
> > =

> > Make sure the line_time_us isn't zero in the gmch watermarks code as
> > that would cause a div by zero. This can be triggered by specifying
> > a very fast pixel clock for the mode.
> =

> Very fast but valid?

74.25 GHz. I'm not sure which way you would classify that :)

> If it was just very fast, we should have rejected
> the mode line.

Except we do more or less zero checks on the mode supplied to the
setcrtc ioctl. Something we should really get fixed at some point.

-- =

Ville Syrj=E4l=E4
Intel OTC