From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Chris Wilson <chris@chris-wilson.co.uk>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/i915: Revert workaround for disabling L3 cache aging on IVB
Date: Mon, 17 Feb 2014 10:59:09 +0200 [thread overview]
Message-ID: <20140217085909.GN3852@intel.com> (raw)
In-Reply-To: <1392417283-26185-1-git-send-email-chris@chris-wilson.co.uk>
On Fri, Feb 14, 2014 at 10:34:43PM +0000, Chris Wilson wrote:
> In commit e4e0c058a19c41150d12ad2d3023b3cf09c5de67
> Author: Eugeni Dodonov <eugeni.dodonov@intel.com>
> Date: Wed Feb 8 12:53:50 2012 -0800
>
> drm/i915: gen7: Implement an L3 caching workaround.
>
> the L3 cache aging was disabled. This was part of a shotgun response
> to a number of GPU hang bugs, but there appears to be no documentation
> to suggest that disabling the L3 cache age was ever required (to prevent
> the GPU hangs).
Bspec still lists the 0xF value in the w/a list, but the actual register
description doesn't say that this bit needs to be set. All the other
bits match either the default values, or specific notes about which bits
need to be set.
So I get the feeling this should be fine:
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Restoring the L3 cache age is a minor performance win of around 2%
> on IVB:GT2. (Note that this value seems to be consistent across a number
> of tests and so appears to be above the usual noise.)
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Kenneth Graunke <kenneth@whitecape.org>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index a2c68c9492ba..d40d71bb66b6 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4171,7 +4171,7 @@
> #define VLV_B0_WA_L3SQCREG1_VALUE 0x00D30000
>
> #define GEN7_L3CNTLREG1 0xB01C
> -#define GEN7_WA_FOR_GEN7_L3_CONTROL 0x3C4FFF8C
> +#define GEN7_WA_FOR_GEN7_L3_CONTROL 0x3C47FF8C
> #define GEN7_L3AGDIS (1<<19)
>
> #define GEN7_L3_CHICKEN_MODE_REGISTER 0xB030
> --
> 1.9.0.rc3
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
next prev parent reply other threads:[~2014-02-17 8:59 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-02-14 22:34 [PATCH] drm/i915: Revert workaround for disabling L3 cache aging on IVB Chris Wilson
2014-02-17 8:59 ` Ville Syrjälä [this message]
2014-03-04 15:48 ` Daniel Vetter
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