From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH 7/5] drm/i915: Improve gen3/4 frame counter Date: Tue, 18 Feb 2014 16:41:02 +0200 Message-ID: <20140218144102.GT3852@intel.com> References: <1392306174-9148-1-git-send-email-ville.syrjala@linux.intel.com> <1392725061-30144-1-git-send-email-ville.syrjala@linux.intel.com> <1392732960.13243.5.camel@intelbox> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTP id B14E9FAB1B for ; Tue, 18 Feb 2014 06:41:32 -0800 (PST) Content-Disposition: inline In-Reply-To: <1392732960.13243.5.camel@intelbox> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org To: Imre Deak Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Tue, Feb 18, 2014 at 04:16:00PM +0200, Imre Deak wrote: > On Tue, 2014-02-18 at 14:04 +0200, ville.syrjala@linux.intel.com wrote: > > From: Ville Syrj=E4l=E4 > > = > > Currently the logic to fix up the frame counter on gen3/4 assumes that > > start of vblank occurs at vblank_start*htotal pixels, when in fact > > it occurs htotal-hsync_start pixels earlier. Apply the appropriate > > adjustment to make the frame counter more accurate. > > = > > Also fix the vblank start position for interlaced display modes. > > = > > Signed-off-by: Ville Syrj=E4l=E4 > > --- > > drivers/gpu/drm/i915/i915_irq.c | 21 ++++++++++++++++----- > > 1 file changed, 16 insertions(+), 5 deletions(-) > > = > > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i91= 5_irq.c > > index 9f1c449..fc49fb6 100644 > > --- a/drivers/gpu/drm/i915/i915_irq.c > > +++ b/drivers/gpu/drm/i915/i915_irq.c > > @@ -639,7 +639,7 @@ static u32 i915_get_vblank_counter(struct drm_devic= e *dev, int pipe) > > drm_i915_private_t *dev_priv =3D (drm_i915_private_t *) dev->dev_priv= ate; > > unsigned long high_frame; > > unsigned long low_frame; > > - u32 high1, high2, low, pixel, vbl_start; > > + u32 high1, high2, low, pixel, vbl_start, hsync_start, htotal; > > = > > if (!i915_pipe_enabled(dev, pipe)) { > > DRM_DEBUG_DRIVER("trying to get vblank count for disabled " > > @@ -653,17 +653,28 @@ static u32 i915_get_vblank_counter(struct drm_dev= ice *dev, int pipe) > > const struct drm_display_mode *mode =3D > > &intel_crtc->config.adjusted_mode; > > = > > - vbl_start =3D mode->crtc_vblank_start * mode->crtc_htotal; > > + htotal =3D mode->crtc_htotal; > > + hsync_start =3D mode->crtc_hsync_start; > > + vbl_start =3D mode->crtc_vblank_start; > > + if (mode->flags & DRM_MODE_FLAG_INTERLACE) > > + vbl_start =3D DIV_ROUND_UP(vbl_start, 2); > = > The adjustment for interlace mode is already done in drm_mode_setcrtc, > so I think we don't need it here. We throw away the values filled in by drm_mode_setcrtc(). Which is a good thing since it rounds the result the wrong way (for our hardware at least). The values we see here are filled in by intel_modeset_pipe_config() which doesn't pass the CRTC_INTERLACE_HALVE_V flag to drm_mode_set_crtcinfo(). > Otherwise this patch makes sense to me > based on the signal chart you drew on this, so: > = > Reviewed-by: Imre Deak > = > > } else { > > enum transcoder cpu_transcoder =3D (enum transcoder) pipe; > > - u32 htotal; > > = > > htotal =3D ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff) + 1; > > + hsync_start =3D (I915_READ(HSYNC(cpu_transcoder)) & 0x1fff) + 1; > > vbl_start =3D (I915_READ(VBLANK(cpu_transcoder)) & 0x1fff) + 1; > > - > > - vbl_start *=3D htotal; > > + if ((I915_READ(PIPECONF(cpu_transcoder)) & > > + PIPECONF_INTERLACE_MASK) !=3D PIPECONF_PROGRESSIVE) > > + vbl_start =3D DIV_ROUND_UP(vbl_start, 2); > > } > > = > > + /* Convert to pixel count */ > > + vbl_start *=3D htotal; > > + > > + /* Start of vblank event occurs at start of hsync */ > > + vbl_start -=3D htotal - hsync_start; > > + > > high_frame =3D PIPEFRAME(pipe); > > low_frame =3D PIPEFRAMEPIXEL(pipe); > > = > = -- = Ville Syrj=E4l=E4 Intel OTC