From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH 19/19] drm/i915: power domains: add vlv power wells Date: Wed, 19 Feb 2014 14:29:44 +0200 Message-ID: <20140219122944.GC3852@intel.com> References: <1392674540-10915-1-git-send-email-imre.deak@intel.com> <1392674540-10915-20-git-send-email-imre.deak@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTP id 46709F9CEA for ; Wed, 19 Feb 2014 04:29:48 -0800 (PST) Content-Disposition: inline In-Reply-To: <1392674540-10915-20-git-send-email-imre.deak@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org To: Imre Deak Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Tue, Feb 18, 2014 at 12:02:20AM +0200, Imre Deak wrote: > Based on an early draft from Jesse. > = > Add support for powering on/off the dynamic power wells on VLV by > registering its display and dpio dynamic power wells with the power > domain framework. > = > For now power on all PHY TX lanes regardless of the actual lane > configuration. Later this can be optimized when the PHY side setup > enables only the required lanes. Atm, it enables all lanes in all > cases. > = > Signed-off-by: Imre Deak > --- > drivers/gpu/drm/i915/i915_dma.c | 1 - > drivers/gpu/drm/i915/i915_drv.h | 2 +- > drivers/gpu/drm/i915/intel_display.c | 1 + > drivers/gpu/drm/i915/intel_pm.c | 228 +++++++++++++++++++++++++++++= ++++++ > 4 files changed, 230 insertions(+), 2 deletions(-) > = > diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_= dma.c > index dca4dc3..f8f7a59 100644 > --- a/drivers/gpu/drm/i915/i915_dma.c > +++ b/drivers/gpu/drm/i915/i915_dma.c > @@ -1668,7 +1668,6 @@ int i915_driver_load(struct drm_device *dev, unsign= ed long flags) > goto out_mtrrfree; > } > = > - dev_priv->display_irqs_enabled =3D true; > intel_irq_init(dev); > intel_uncore_sanitize(dev); > = > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_= drv.h > index 227c349..804334e 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -1053,7 +1053,7 @@ struct i915_power_well { > /* power well enable/disable usage count */ > int count; > unsigned long domains; > - void *data; > + unsigned long data; > const struct i915_power_well_ops *ops; > }; > = > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/= intel_display.c > index ea00878..d6661c4 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -4224,6 +4224,7 @@ static void valleyview_modeset_global_resources(str= uct drm_device *dev) > = > if (req_cdclk !=3D cur_cdclk) > valleyview_set_cdclk(dev, req_cdclk); > + modeset_update_power_wells(dev); > } > = > static void valleyview_crtc_enable(struct drm_crtc *crtc) > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel= _pm.c > index 68f58e5..e4416a7 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -5344,6 +5344,133 @@ static void hsw_power_well_disable(struct drm_i91= 5_private *dev_priv, > hsw_enable_package_c8(dev_priv); > } > = > +static void vlv_set_power_well(struct drm_i915_private *dev_priv, > + struct i915_power_well *power_well, bool enable) > +{ > + enum punit_power_well power_well_id =3D power_well->data; > + u32 mask; > + u32 state; > + u32 ctrl; > + > + mask =3D PUNIT_PWRGT_MASK(power_well_id); > + state =3D enable ? PUNIT_PWRGT_PWR_ON(power_well_id) : > + PUNIT_PWRGT_PWR_GATE(power_well_id); > + > + mutex_lock(&dev_priv->rps.hw_lock); > + > +#define COND \ > + ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) =3D=3D state) > + > + if (COND) > + goto out; > + > + ctrl =3D vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL); > + ctrl &=3D ~mask; > + ctrl |=3D state; > + vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl); > + > + if (wait_for(COND, 100)) > + DRM_ERROR("timout setting power well state %08x (%08x)\n", > + state, > + vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL)); #undef COND somewhere to avoid suprises further down in the code? > + > +out: > + mutex_unlock(&dev_priv->rps.hw_lock); > +} > + -- = Ville Syrj=E4l=E4 Intel OTC