[PATCH 6/6] drm/i915: Save color manager status

Shashank Sharma
2014-02-20T12:34:54Z

This patch adds functions:
1. save_color_manager_status: to save color manager
correction values during a display suspend and
2. restore_color_manager_status: to restore color
correction values during display resume time.

This will help to give consistent color correction across
suspend resume cycles

Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
Signed-off-by: Vikas Korjani <vikas.korjani@intel.com>
---
drivers/gpu/drm/i915/intel_clrmgr.c | 113 +++++++++++++++++++++++++++++++++++
drivers/gpu/drm/i915/intel_clrmgr.h | 2 +-
2 files changed, 114 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_clrmgr.c b/drivers/gpu/drm/i915/intel_clrmgr.c
index 9d2203e..bb5d072 100644
--- a/drivers/gpu/drm/i915/intel_clrmgr.c
+++ b/drivers/gpu/drm/i915/intel_clrmgr.c
@@ -926,6 +926,119 @@ static bool intel_clrmgr_disable_property(struct drm_device *dev,
return true;
}

+
+/* Apply saved values of contrast/brightness */
+static bool intel_restore_cb(struct drm_device *dev)
+{
+ int count = 0;
+
+ while (count < VLV_NO_SPRITE_REG) {
+ if (intel_sprite_cb_adjust(dev, &saved_cbvals[count++])) {
+ DRM_ERROR("Color Restore: Error restoring CB\n");
+ return false;
+ }
+ }
+ return true;
+}
+
+/* Apply saved values of hue/saturation */
+static bool intel_restore_hs(struct drm_device *dev)
+{
+ int count = 0;
+
+ while (count < VLV_NO_SPRITE_REG) {
+ if (intel_sprite_hs_adjust(dev, &saved_hsvals[count++])) {
+ DRM_ERROR("Color Restore: Error restoring HS\n");
+ return false;
+ }
+ }
+ return true;
+}
+
+/* Sustain color manager corrections across suspend/resume */
+bool intel_restore_clr_mgr_status(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct clrmgr_pipe_status *pstatus = dev_priv->clrmgr_status.pstatus;
+
+ /* Validate input */
+ if (!dev_priv) {
+ DRM_ERROR("Color Restore: Invalid input\n");
+ return false;
+ }
+
+ /* If gamma enabled, restore gamma */
+ if (pstatus->gamma_enabled) {
+ if (intel_clrmgr_enable_gamma(dev, pipe_a)) {
+ DRM_ERROR("Color Restore: gamma failed\n");
+ return false;
+ }
+ }
+
+ /* If csc enabled, restore csc */
+ if (pstatus->csc_enabled) {
+ if (intel_clrmgr_enable_csc(dev, pipe_a)) {
+ DRM_ERROR("Color Restore: CSC failed\n");
+ return false;
+ }
+ }
+
+ /* Restore hue staturation */
+ if (pstatus->hs_enabled) {
+ if (!intel_restore_hs(dev)) {
+ DRM_ERROR("Color Restore: Restore hue/sat failed\n");
+ return false;
+ }
+ }
+
+ /* Restore contrast brightness */
+ if (pstatus->cb_enabled) {
+ if (!intel_restore_cb(dev)) {
+ DRM_ERROR("Color Restore: Restore CB failed\n");
+ return false;
+ }
+ }
+
+ DRM_DEBUG("Color Restore: Restore success\n");
+ return true;
+}
+EXPORT_SYMBOL(intel_restore_clr_mgr_status);
+
+/* Save current contrast brightness values */
+void intel_save_cb_status(struct drm_device *dev)
+{
+ int count = 0;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+
+ while (count <= VLV_NO_SPRITE_REG) {
+ saved_cbvals[count].val =
+ I915_READ(GET_SPRITE_HS(count));
+ count++;
+ }
+}
+
+/* Save current hue saturation values */
+void intel_save_hs_status(struct drm_device *dev)
+{
+ int count = 0;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+
+ while (count <= VLV_NO_SPRITE_REG) {
+ saved_hsvals[count].val =
+ I915_READ(GET_SPRITE_CB(count));
+ count++;
+ }
+}
+
+/* Save the required register values to be restored */
+void intel_save_clr_mgr_status(struct drm_device *dev)
+{
+ intel_save_hs_status(dev);
+ intel_save_cb_status(dev);
+}
+EXPORT_SYMBOL(intel_save_clr_mgr_status);
+
+
/*
* _parse_clrmgr_data: Extract the data from color manager buffer
* The data parser follows a strict grammar.
diff --git a/drivers/gpu/drm/i915/intel_clrmgr.h b/drivers/gpu/drm/i915/intel_clrmgr.h
index 25d3491..6fe0592 100644
--- a/drivers/gpu/drm/i915/intel_clrmgr.h
+++ b/drivers/gpu/drm/i915/intel_clrmgr.h
@@ -45,7 +45,7 @@ struct hue_saturationlut {
/* General defines */
#define CLR_MGR_PARSE_MAX 256
#define CLR_MGR_PARSE_MIN 1
-#define VLV_NO_SPRITE_REG 4
+#define VLV_NO_SPRITE_REG 4
#define SIZE_STATUS 10
#define CLR_EDID_PROPERTY 2
#define CLR_EDID_ENABLE (CLR_EDID_PROPERTY + 2)
--
1.7.10.4