From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH 05/13] drm/i915: gen specific ring init Date: Mon, 24 Feb 2014 15:05:46 +0200 Message-ID: <20140224130546.GO3852@intel.com> References: <1392877166-9195-1-git-send-email-benjamin.widawsky@intel.com> <1392877166-9195-5-git-send-email-benjamin.widawsky@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTP id F078FFAA2E for ; Mon, 24 Feb 2014 05:05:59 -0800 (PST) Content-Disposition: inline In-Reply-To: <1392877166-9195-5-git-send-email-benjamin.widawsky@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org To: Ben Widawsky Cc: Intel GFX , Ben Widawsky List-Id: intel-gfx@lists.freedesktop.org On Wed, Feb 19, 2014 at 10:19:18PM -0800, Ben Widawsky wrote: > Gen8 has already had some differentiation with how it handles rings. > Semaphores bring yet more differences, and now is as good a time as any > to do the split. > = > Also, since gen8 doesn't actually use semaphores up until this point, > put the proper "NULL" values in for the mbox info. > = > v2: v1 had a stale commit message > = > v3: Move everything in the is_semaphore_enabled() check > = > Signed-off-by: Ben Widawsky > --- > drivers/gpu/drm/i915/intel_ringbuffer.c | 142 ++++++++++++++++++++++----= ------ > 1 file changed, 97 insertions(+), 45 deletions(-) > = > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i9= 15/intel_ringbuffer.c > index bf061dd..691da67 100644 > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c > @@ -1870,19 +1870,34 @@ int intel_init_render_ring_buffer(struct drm_devi= ce *dev) > ring->id =3D RCS; > ring->mmio_base =3D RENDER_RING_BASE; > = > - if (INTEL_INFO(dev)->gen >=3D 6) { > + if (INTEL_INFO(dev)->gen >=3D 8) { > + ring->add_request =3D gen6_add_request; > + ring->flush =3D gen8_render_ring_flush; > + ring->irq_get =3D gen8_ring_get_irq; > + ring->irq_put =3D gen8_ring_put_irq; > + ring->irq_enable_mask =3D GT_RENDER_USER_INTERRUPT; > + ring->get_seqno =3D gen6_ring_get_seqno; > + ring->set_seqno =3D ring_set_seqno; > + if (i915_semaphore_is_enabled(dev)) { > + ring->semaphore.sync_to =3D gen6_ring_sync; > + ring->semaphore.signal =3D gen6_signal; > + ring->semaphore.signal =3D gen6_signal; Double assignment. > + ring->semaphore.mbox.wait[RCS] =3D MI_SEMAPHORE_SYNC_INVALID; > + ring->semaphore.mbox.wait[VCS] =3D MI_SEMAPHORE_SYNC_INVALID; > + ring->semaphore.mbox.wait[BCS] =3D MI_SEMAPHORE_SYNC_INVALID; > + ring->semaphore.mbox.wait[VECS] =3D MI_SEMAPHORE_SYNC_INVALID; > + ring->semaphore.mbox.signal[RCS] =3D GEN6_NOSYNC; > + ring->semaphore.mbox.signal[VCS] =3D GEN6_NOSYNC; > + ring->semaphore.mbox.signal[BCS] =3D GEN6_NOSYNC; > + ring->semaphore.mbox.signal[VECS] =3D GEN6_NOSYNC; > + } > + } else if (INTEL_INFO(dev)->gen >=3D 6) { > ring->add_request =3D gen6_add_request; > ring->flush =3D gen7_render_ring_flush; > if (INTEL_INFO(dev)->gen =3D=3D 6) > ring->flush =3D gen6_render_ring_flush; > - if (INTEL_INFO(dev)->gen >=3D 8) { > - ring->flush =3D gen8_render_ring_flush; > - ring->irq_get =3D gen8_ring_get_irq; > - ring->irq_put =3D gen8_ring_put_irq; > - } else { > - ring->irq_get =3D gen6_ring_get_irq; > - ring->irq_put =3D gen6_ring_put_irq; > - } > + ring->irq_get =3D gen6_ring_get_irq; > + ring->irq_put =3D gen6_ring_put_irq; > ring->irq_enable_mask =3D GT_RENDER_USER_INTERRUPT; > ring->get_seqno =3D gen6_ring_get_seqno; > ring->set_seqno =3D ring_set_seqno; > @@ -1925,6 +1940,7 @@ int intel_init_render_ring_buffer(struct drm_device= *dev) > ring->irq_enable_mask =3D I915_USER_INTERRUPT; > } > ring->write_tail =3D ring_write_tail; > + > if (IS_HASWELL(dev)) > ring->dispatch_execbuffer =3D hsw_ring_dispatch_execbuffer; > else if (IS_GEN8(dev)) > @@ -2058,24 +2074,36 @@ int intel_init_bsd_ring_buffer(struct drm_device = *dev) > ring->irq_put =3D gen8_ring_put_irq; > ring->dispatch_execbuffer =3D > gen8_ring_dispatch_execbuffer; > + if (i915_semaphore_is_enabled(dev)) { > + ring->semaphore.sync_to =3D gen6_ring_sync; > + ring->semaphore.signal =3D gen6_signal; > + ring->semaphore.mbox.wait[RCS] =3D MI_SEMAPHORE_SYNC_INVALID; > + ring->semaphore.mbox.wait[VCS] =3D MI_SEMAPHORE_SYNC_INVALID; > + ring->semaphore.mbox.wait[BCS] =3D MI_SEMAPHORE_SYNC_INVALID; > + ring->semaphore.mbox.wait[VECS] =3D MI_SEMAPHORE_SYNC_INVALID; > + ring->semaphore.mbox.signal[RCS] =3D GEN6_NOSYNC; > + ring->semaphore.mbox.signal[VCS] =3D GEN6_NOSYNC; > + ring->semaphore.mbox.signal[BCS] =3D GEN6_NOSYNC; > + ring->semaphore.mbox.signal[VECS] =3D GEN6_NOSYNC; > + } > } else { > ring->irq_enable_mask =3D GT_BSD_USER_INTERRUPT; > ring->irq_get =3D gen6_ring_get_irq; > ring->irq_put =3D gen6_ring_put_irq; > ring->dispatch_execbuffer =3D > gen6_ring_dispatch_execbuffer; > - } > - if (i915_semaphore_is_enabled(dev)) { > - ring->semaphore.sync_to =3D gen6_ring_sync; > - ring->semaphore.signal =3D gen6_signal; > - ring->semaphore.mbox.wait[RCS] =3D MI_SEMAPHORE_SYNC_VR; > - ring->semaphore.mbox.wait[VCS] =3D MI_SEMAPHORE_SYNC_INVALID; > - ring->semaphore.mbox.wait[BCS] =3D MI_SEMAPHORE_SYNC_VB; > - ring->semaphore.mbox.wait[VECS] =3D MI_SEMAPHORE_SYNC_VVE; > - ring->semaphore.mbox.signal[RCS] =3D GEN6_RVSYNC; > - ring->semaphore.mbox.signal[VCS] =3D GEN6_NOSYNC; > - ring->semaphore.mbox.signal[BCS] =3D GEN6_BVSYNC; > - ring->semaphore.mbox.signal[VECS] =3D GEN6_VEVSYNC; > + if (i915_semaphore_is_enabled(dev)) { > + ring->semaphore.sync_to =3D gen6_ring_sync; > + ring->semaphore.signal =3D gen6_signal; > + ring->semaphore.mbox.wait[RCS] =3D MI_SEMAPHORE_SYNC_VR; > + ring->semaphore.mbox.wait[VCS] =3D MI_SEMAPHORE_SYNC_INVALID; > + ring->semaphore.mbox.wait[BCS] =3D MI_SEMAPHORE_SYNC_VB; > + ring->semaphore.mbox.wait[VECS] =3D MI_SEMAPHORE_SYNC_VVE; > + ring->semaphore.mbox.signal[RCS] =3D GEN6_RVSYNC; > + ring->semaphore.mbox.signal[VCS] =3D GEN6_NOSYNC; > + ring->semaphore.mbox.signal[BCS] =3D GEN6_BVSYNC; > + ring->semaphore.mbox.signal[VECS] =3D GEN6_VEVSYNC; > + } > } > } else { > ring->mmio_base =3D BSD_RING_BASE; > @@ -2119,23 +2147,35 @@ int intel_init_blt_ring_buffer(struct drm_device = *dev) > ring->irq_get =3D gen8_ring_get_irq; > ring->irq_put =3D gen8_ring_put_irq; > ring->dispatch_execbuffer =3D gen8_ring_dispatch_execbuffer; > + if (i915_semaphore_is_enabled(dev)) { > + ring->semaphore.sync_to =3D gen6_ring_sync; > + ring->semaphore.signal =3D gen6_signal; > + ring->semaphore.mbox.wait[RCS] =3D MI_SEMAPHORE_SYNC_INVALID; > + ring->semaphore.mbox.wait[VCS] =3D MI_SEMAPHORE_SYNC_INVALID; > + ring->semaphore.mbox.wait[BCS] =3D MI_SEMAPHORE_SYNC_INVALID; > + ring->semaphore.mbox.wait[VECS] =3D MI_SEMAPHORE_SYNC_INVALID; > + ring->semaphore.mbox.signal[RCS] =3D GEN6_NOSYNC; > + ring->semaphore.mbox.signal[VCS] =3D GEN6_NOSYNC; > + ring->semaphore.mbox.signal[BCS] =3D GEN6_NOSYNC; > + ring->semaphore.mbox.signal[VECS] =3D GEN6_NOSYNC; > + } > } else { > ring->irq_enable_mask =3D GT_BLT_USER_INTERRUPT; > ring->irq_get =3D gen6_ring_get_irq; > ring->irq_put =3D gen6_ring_put_irq; > ring->dispatch_execbuffer =3D gen6_ring_dispatch_execbuffer; > - } > - if (i915_semaphore_is_enabled(dev)) { > - ring->semaphore.signal =3D gen6_signal; > - ring->semaphore.sync_to =3D gen6_ring_sync; > - ring->semaphore.mbox.wait[RCS] =3D MI_SEMAPHORE_SYNC_BR; > - ring->semaphore.mbox.wait[VCS] =3D MI_SEMAPHORE_SYNC_BV; > - ring->semaphore.mbox.wait[BCS] =3D MI_SEMAPHORE_SYNC_INVALID; > - ring->semaphore.mbox.wait[VECS] =3D MI_SEMAPHORE_SYNC_BVE; > - ring->semaphore.mbox.signal[RCS] =3D GEN6_RBSYNC; > - ring->semaphore.mbox.signal[VCS] =3D GEN6_VBSYNC; > - ring->semaphore.mbox.signal[BCS] =3D GEN6_NOSYNC; > - ring->semaphore.mbox.signal[VECS] =3D GEN6_VEBSYNC; > + if (i915_semaphore_is_enabled(dev)) { > + ring->semaphore.signal =3D gen6_signal; > + ring->semaphore.sync_to =3D gen6_ring_sync; > + ring->semaphore.mbox.wait[RCS] =3D MI_SEMAPHORE_SYNC_BR; > + ring->semaphore.mbox.wait[VCS] =3D MI_SEMAPHORE_SYNC_BV; > + ring->semaphore.mbox.wait[BCS] =3D MI_SEMAPHORE_SYNC_INVALID; > + ring->semaphore.mbox.wait[VECS] =3D MI_SEMAPHORE_SYNC_BVE; > + ring->semaphore.mbox.signal[RCS] =3D GEN6_RBSYNC; > + ring->semaphore.mbox.signal[VCS] =3D GEN6_VBSYNC; > + ring->semaphore.mbox.signal[BCS] =3D GEN6_NOSYNC; > + ring->semaphore.mbox.signal[VECS] =3D GEN6_VEBSYNC; > + } > } > ring->init =3D init_ring_common; > = > @@ -2163,23 +2203,35 @@ int intel_init_vebox_ring_buffer(struct drm_devic= e *dev) > ring->irq_get =3D gen8_ring_get_irq; > ring->irq_put =3D gen8_ring_put_irq; > ring->dispatch_execbuffer =3D gen8_ring_dispatch_execbuffer; > + if (i915_semaphore_is_enabled(dev)) { > + ring->semaphore.sync_to =3D gen6_ring_sync; > + ring->semaphore.signal =3D gen6_signal; > + ring->semaphore.mbox.wait[RCS] =3D MI_SEMAPHORE_SYNC_INVALID; > + ring->semaphore.mbox.wait[VCS] =3D MI_SEMAPHORE_SYNC_INVALID; > + ring->semaphore.mbox.wait[BCS] =3D MI_SEMAPHORE_SYNC_INVALID; > + ring->semaphore.mbox.wait[VECS] =3D MI_SEMAPHORE_SYNC_INVALID; > + ring->semaphore.mbox.signal[RCS] =3D GEN6_NOSYNC; > + ring->semaphore.mbox.signal[VCS] =3D GEN6_NOSYNC; > + ring->semaphore.mbox.signal[BCS] =3D GEN6_NOSYNC; > + ring->semaphore.mbox.signal[VECS] =3D GEN6_NOSYNC; > + } > } else { > ring->irq_enable_mask =3D PM_VEBOX_USER_INTERRUPT; > ring->irq_get =3D hsw_vebox_get_irq; > ring->irq_put =3D hsw_vebox_put_irq; > ring->dispatch_execbuffer =3D gen6_ring_dispatch_execbuffer; > - } > - if (i915_semaphore_is_enabled(dev)) { > - ring->semaphore.sync_to =3D gen6_ring_sync; > - ring->semaphore.signal =3D gen6_signal; > - ring->semaphore.mbox.wait[RCS] =3D MI_SEMAPHORE_SYNC_VER; > - ring->semaphore.mbox.wait[VCS] =3D MI_SEMAPHORE_SYNC_VEV; > - ring->semaphore.mbox.wait[BCS] =3D MI_SEMAPHORE_SYNC_VEB; > - ring->semaphore.mbox.wait[VECS] =3D MI_SEMAPHORE_SYNC_INVALID; > - ring->semaphore.mbox.signal[RCS] =3D GEN6_RVESYNC; > - ring->semaphore.mbox.signal[VCS] =3D GEN6_VVESYNC; > - ring->semaphore.mbox.signal[BCS] =3D GEN6_BVESYNC; > - ring->semaphore.mbox.signal[VECS] =3D GEN6_NOSYNC; > + if (i915_semaphore_is_enabled(dev)) { > + ring->semaphore.sync_to =3D gen6_ring_sync; > + ring->semaphore.signal =3D gen6_signal; > + ring->semaphore.mbox.wait[RCS] =3D MI_SEMAPHORE_SYNC_VER; > + ring->semaphore.mbox.wait[VCS] =3D MI_SEMAPHORE_SYNC_VEV; > + ring->semaphore.mbox.wait[BCS] =3D MI_SEMAPHORE_SYNC_VEB; > + ring->semaphore.mbox.wait[VECS] =3D MI_SEMAPHORE_SYNC_INVALID; > + ring->semaphore.mbox.signal[RCS] =3D GEN6_RVESYNC; > + ring->semaphore.mbox.signal[VCS] =3D GEN6_VVESYNC; > + ring->semaphore.mbox.signal[BCS] =3D GEN6_BVESYNC; > + ring->semaphore.mbox.signal[VECS] =3D GEN6_NOSYNC; > + } > } > ring->init =3D init_ring_common; > = > -- = > 1.9.0 -- = Ville Syrj=E4l=E4 Intel OTC