From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH 10/13] drm/i915/bdw: collect semaphore error state Date: Mon, 24 Feb 2014 15:08:04 +0200 Message-ID: <20140224130804.GQ3852@intel.com> References: <1392877166-9195-1-git-send-email-benjamin.widawsky@intel.com> <1392877166-9195-10-git-send-email-benjamin.widawsky@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTP id A6CCDFAA4D for ; Mon, 24 Feb 2014 05:08:08 -0800 (PST) Content-Disposition: inline In-Reply-To: <1392877166-9195-10-git-send-email-benjamin.widawsky@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org To: Ben Widawsky Cc: Intel GFX , Ben Widawsky List-Id: intel-gfx@lists.freedesktop.org On Wed, Feb 19, 2014 at 10:19:23PM -0800, Ben Widawsky wrote: > Since the semaphore information is in an object, just dump it, and let > the user parse it later. > = > NOTE: The page being used for the semaphores are incoherent with the > CPU. No matter what I do, I cannot figure out a way to read anything but > 0s. Note that the semaphore waits are indeed working. > = > v2: Don't print signal, and wait (they should be the same). Instead, > print sync_seqno (Chris) > = > v3: Free the semaphore error object (Chris) > = > v4: Fix semaphore offset calculation during error state collection > (Ville) > = > Signed-off-by: Ben Widawsky > --- > drivers/gpu/drm/i915/i915_drv.h | 1 + > drivers/gpu/drm/i915/i915_gpu_error.c | 52 +++++++++++++++++++++++++++= +++--- > drivers/gpu/drm/i915/intel_ringbuffer.h | 12 ++++---- > 3 files changed, 55 insertions(+), 10 deletions(-) > = > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_= drv.h > index 028ce5a..9b86874 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -322,6 +322,7 @@ struct drm_i915_error_state { > u64 fence[I915_MAX_NUM_FENCES]; > struct intel_overlay_error_state *overlay; > struct intel_display_error_state *display; > + struct drm_i915_error_object *semaphore_obj; > = > struct drm_i915_error_ring { > bool valid; > diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915= /i915_gpu_error.c > index 2b64493..25fc2ea 100644 > --- a/drivers/gpu/drm/i915/i915_gpu_error.c > +++ b/drivers/gpu/drm/i915/i915_gpu_error.c > @@ -310,6 +310,7 @@ int i915_error_state_to_str(struct drm_i915_error_sta= te_buf *m, > struct drm_device *dev =3D error_priv->dev; > drm_i915_private_t *dev_priv =3D dev->dev_private; > struct drm_i915_error_state *error =3D error_priv->error; > + struct drm_i915_error_object *obj; > int i, j, page, offset, elt; > = > if (!error) { > @@ -360,8 +361,6 @@ int i915_error_state_to_str(struct drm_i915_error_sta= te_buf *m, > error->pinned_bo_count[0]); > = > for (i =3D 0; i < ARRAY_SIZE(error->ring); i++) { > - struct drm_i915_error_object *obj; > - > if ((obj =3D error->ring[i].batchbuffer)) { > err_printf(m, "%s --- gtt_offset =3D 0x%08x\n", > dev_priv->ring[i].name, > @@ -436,6 +435,19 @@ int i915_error_state_to_str(struct drm_i915_error_st= ate_buf *m, > } > } > = > + obj =3D error->semaphore_obj; > + if (obj) { Still won't pass under Chris's consitency radar. > + err_printf(m, "Semaphore page =3D 0x%08x\n", obj->gtt_offset); > + for (elt =3D 0; elt < PAGE_SIZE/16; elt +=3D 4) { > + err_printf(m, "[%04x] %08x %08x %08x %08x\n", > + elt * 4, > + obj->pages[0][elt], > + obj->pages[0][elt+1], > + obj->pages[0][elt+2], > + obj->pages[0][elt+3]); > + } > + } > + > if (error->overlay) > intel_overlay_print_error_state(m, error->overlay); > = > @@ -506,6 +518,7 @@ static void i915_error_state_free(struct kref *error_= ref) > kfree(error->ring[i].requests); > } > = > + i915_error_object_free(error->semaphore_obj); > kfree(error->active_bo); > kfree(error->overlay); > kfree(error->display); > @@ -797,6 +810,33 @@ i915_error_first_batchbuffer(struct drm_i915_private= *dev_priv, > return NULL; > } > = > +static void gen8_record_semaphore_state(struct drm_i915_private *dev_pri= v, > + struct drm_i915_error_state *error, > + struct intel_ring_buffer *ring, > + struct drm_i915_error_ring *ering) > +{ > + struct intel_ring_buffer *useless; > + int i; > + > + if (!i915_semaphore_is_enabled(dev_priv->dev)) > + return; > + > + if (!error->semaphore_obj) > + error->semaphore_obj =3D > + i915_error_object_create(dev_priv, > + dev_priv->semaphore_obj, > + &dev_priv->gtt.base); > + > + for_each_ring(useless, dev_priv, i) { > + u16 signal_offset =3D > + (GEN8_SIGNAL_OFFSET(ring, i) / 4) & PAGE_MASK; (... & PAGE_MASK) / 4; > + u32 *tmp =3D error->semaphore_obj->pages[0]; > + > + ering->semaphore_mboxes[i] =3D tmp[signal_offset]; > + ering->semaphore_seqno[i] =3D ring->semaphore.sync_seqno[i]; > + } > +} > + > static void gen6_record_semaphore_state(struct drm_i915_private *dev_pri= v, > struct intel_ring_buffer *ring, > struct drm_i915_error_ring *ering) > @@ -814,6 +854,7 @@ static void gen6_record_semaphore_state(struct drm_i9= 15_private *dev_priv, > } > = > static void i915_record_ring_state(struct drm_device *dev, > + struct drm_i915_error_state *error, > struct intel_ring_buffer *ring, > struct drm_i915_error_ring *ering) > { > @@ -822,7 +863,10 @@ static void i915_record_ring_state(struct drm_device= *dev, > if (INTEL_INFO(dev)->gen >=3D 6) { > ering->rc_psmi =3D I915_READ(ring->mmio_base + 0x50); > ering->fault_reg =3D I915_READ(RING_FAULT_REG(ring)); > - gen6_record_semaphore_state(dev_priv, ring, ering); > + if (INTEL_INFO(dev)->gen >=3D 8) > + gen8_record_semaphore_state(dev_priv, error, ring, ering); > + else > + gen6_record_semaphore_state(dev_priv, ring, ering); > } > = > if (INTEL_INFO(dev)->gen >=3D 4) { > @@ -948,7 +992,7 @@ static void i915_gem_record_rings(struct drm_device *= dev, > = > error->ring[i].valid =3D true; > = > - i915_record_ring_state(dev, ring, &error->ring[i]); > + i915_record_ring_state(dev, error, ring, &error->ring[i]); > = > error->ring[i].batchbuffer =3D > i915_error_first_batchbuffer(dev_priv, ring); > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i9= 15/intel_ringbuffer.h > index 5d56c95..01aad54 100644 > --- a/drivers/gpu/drm/i915/intel_ringbuffer.h > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h > @@ -37,9 +37,9 @@ struct intel_hw_status_page { > * do the writes, and that must have qw aligned offsets, simply pretend = it's 8b. > */ > #define i915_semaphore_seqno_size sizeof(uint64_t) > -#define GEN8_SIGNAL_OFFSET(to) \ > +#define GEN8_SIGNAL_OFFSET(__ring, to) \ > (i915_gem_obj_ggtt_offset(dev_priv->semaphore_obj) + \ > - (ring->id * I915_NUM_RINGS * i915_semaphore_seqno_size) + \ > + ((__ring)->id * I915_NUM_RINGS * i915_semaphore_seqno_size) + \ > (i915_semaphore_seqno_size * (to))) > = > #define GEN8_WAIT_OFFSET(__ring, from) \ > @@ -51,10 +51,10 @@ struct intel_hw_status_page { > if (!dev_priv->semaphore_obj) { \ > break; \ > } \ > - ring->semaphore.signal_ggtt[RCS] =3D GEN8_SIGNAL_OFFSET(RCS); \ > - ring->semaphore.signal_ggtt[VCS] =3D GEN8_SIGNAL_OFFSET(VCS); \ > - ring->semaphore.signal_ggtt[BCS] =3D GEN8_SIGNAL_OFFSET(BCS); \ > - ring->semaphore.signal_ggtt[VECS] =3D GEN8_SIGNAL_OFFSET(VECS); \ > + ring->semaphore.signal_ggtt[RCS] =3D GEN8_SIGNAL_OFFSET(ring, RCS); \ > + ring->semaphore.signal_ggtt[VCS] =3D GEN8_SIGNAL_OFFSET(ring, VCS); \ > + ring->semaphore.signal_ggtt[BCS] =3D GEN8_SIGNAL_OFFSET(ring, BCS); \ > + ring->semaphore.signal_ggtt[VECS] =3D GEN8_SIGNAL_OFFSET(ring, VECS); \ > ring->semaphore.signal_ggtt[ring->id] =3D MI_SEMAPHORE_SYNC_INVALID; \ > } while(0) > = > -- = > 1.9.0 -- = Ville Syrj=E4l=E4 Intel OTC