From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH 04/13] drm/i915: Make semaphore updates more precise Date: Mon, 24 Feb 2014 15:09:03 +0200 Message-ID: <20140224130903.GR3852@intel.com> References: <1392877166-9195-1-git-send-email-benjamin.widawsky@intel.com> <1392877166-9195-4-git-send-email-benjamin.widawsky@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTP id EDC3CFAA55 for ; Mon, 24 Feb 2014 05:09:06 -0800 (PST) Content-Disposition: inline In-Reply-To: <1392877166-9195-4-git-send-email-benjamin.widawsky@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org To: Ben Widawsky Cc: Intel GFX , Ben Widawsky List-Id: intel-gfx@lists.freedesktop.org On Wed, Feb 19, 2014 at 10:19:17PM -0800, Ben Widawsky wrote: > With the ring mask we now have an easy way to know the number of rings > in the system, and therefore can accurately predict the number of dwords > to emit for semaphore signalling. This was not possible (easily) > previously. > = > There should be no functional impact, simply fewer instructions emitted. > = > While we're here, simply do the round up to 2 instead of the fancier > rounding we did before, which rounding up per mbox, ie 4. This also > allows us to drop the unnecessary MI_NOOP, so not really 4, 3. > = > v2: Use 3 dwords instead of 4 (Ville) > Do the proper calculation to get the number of dwords to emit (Ville) > Conditionally set .sync_to when semaphores are enabled (Ville) > = > Reviewed-by: Ville Syrj=E4l=E4 > Signed-off-by: Ben Widawsky > --- > drivers/gpu/drm/i915/intel_ringbuffer.c | 119 +++++++++++++++++---------= ------ > 1 file changed, 62 insertions(+), 57 deletions(-) > = > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i9= 15/intel_ringbuffer.c > index 06d849a..bf061dd 100644 > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c > @@ -637,24 +637,19 @@ static void render_ring_cleanup(struct intel_ring_b= uffer *ring) > static int gen6_signal(struct intel_ring_buffer *signaller, > unsigned int num_dwords) > { > +#define MBOX_UPDATE_DWORDS 3 > struct drm_device *dev =3D signaller->dev; > struct drm_i915_private *dev_priv =3D dev->dev_private; > struct intel_ring_buffer *useless; > - int i, ret; > + int i, ret, num_rings; > = > - /* NB: In order to be able to do semaphore MBOX updates for varying > - * number of rings, it's easiest if we round up each individual update > - * to a multiple of 2 (since ring updates must always be a multiple of > - * 2) even though the actual update only requires 3 dwords. > - */ > -#define MBOX_UPDATE_DWORDS 4 > - if (i915_semaphore_is_enabled(dev)) > - num_dwords +=3D ((I915_NUM_RINGS-1) * MBOX_UPDATE_DWORDS); > + num_rings =3D hweight_long(INTEL_INFO(dev)->ring_mask); hweight32() would be enough. -- = Ville Syrj=E4l=E4 Intel OTC