From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH 2/2] drm/i915: Add thread stall DOP clock gating workaround on Broadwell. Date: Thu, 27 Feb 2014 11:08:24 +0200 Message-ID: <20140227090824.GJ3852@intel.com> References: <1393487971-739-1-git-send-email-kenneth@whitecape.org> <1393487971-739-2-git-send-email-kenneth@whitecape.org> <20140227084333.GH3852@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTP id 70C41FB5C3 for ; Thu, 27 Feb 2014 01:08:40 -0800 (PST) Content-Disposition: inline In-Reply-To: <20140227084333.GH3852@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org To: Kenneth Graunke Cc: intel-gfx@lists.freedesktop.org, ben@bwidawsk.net List-Id: intel-gfx@lists.freedesktop.org On Thu, Feb 27, 2014 at 10:43:34AM +0200, Ville Syrj=E4l=E4 wrote: > On Wed, Feb 26, 2014 at 11:59:31PM -0800, Kenneth Graunke wrote: > > Ben and I believe this will be necessary on production hardware. > > = > > Signed-off-by: Kenneth Graunke > > --- > > drivers/gpu/drm/i915/i915_reg.h | 1 + > > drivers/gpu/drm/i915/intel_pm.c | 4 ++++ > > 2 files changed, 5 insertions(+) > > = > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i91= 5_reg.h > > index f36d5e0..ade1d71 100644 > > --- a/drivers/gpu/drm/i915/i915_reg.h > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > @@ -5052,6 +5052,7 @@ > > = > > #define GEN8_ROW_CHICKEN 0xe4f0 > > #define PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE (1<<8) > > +#define STALL_DOP_GATING_DISABLE (1<<5) > > = > > #define GEN7_ROW_CHICKEN2 0xe4f4 > > #define GEN7_ROW_CHICKEN2_GT2 0xf4f4 > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/int= el_pm.c > > index df8ad21..226591d 100644 > > --- a/drivers/gpu/drm/i915/intel_pm.c > > +++ b/drivers/gpu/drm/i915/intel_pm.c > > @@ -4842,6 +4842,10 @@ static void gen8_init_clock_gating(struct drm_de= vice *dev) > > I915_WRITE(GEN8_ROW_CHICKEN, > > _MASKED_BIT_ENABLE(PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE)); > > = > > + /* WaDisableThreadStallDopClockGating:bdw */ > > + I915_WRITE(GEN8_ROW_CHICKEN, > > + _MASKED_BIT_ENABLE(STALL_DOP_GATING_DISABLE)); > = > The spec and w/a database are a bit confused on this, but I get the > impression that you're correct. So: > = > Reviewed-by: Ville Syrj=E4l=E4 Actually I might have to take that back a bit. Looks more like it shouldn't be needed for production hardware, but I'm guessing people currently have hardware that needs it, so we should have it at least for now. > = > > + > > /* > > * This GEN8_CENTROID_PIXEL_OPT_DIS W/A is only needed for > > * pre-production hardware > > -- = > > 1.8.4.2 > > = > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > http://lists.freedesktop.org/mailman/listinfo/intel-gfx > = > -- = > Ville Syrj=E4l=E4 > Intel OTC -- = Ville Syrj=E4l=E4 Intel OTC