From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [PATCH 08/19] drm/i915: get port power domain in connector detect Date: Wed, 5 Mar 2014 11:15:29 +0100 Message-ID: <20140305101529.GQ17001@phenom.ffwll.local> References: <1392674540-10915-1-git-send-email-imre.deak@intel.com> <1392674540-10915-9-git-send-email-imre.deak@intel.com> <20140219123508.GD3852@intel.com> <1392813598.19792.1.camel@intelbox> <20140220113337.41a117a3@jbarnes-desktop> <1393242980.13131.47.camel@intelbox> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mail-ee0-f41.google.com (mail-ee0-f41.google.com [74.125.83.41]) by gabe.freedesktop.org (Postfix) with ESMTP id C3056FA481 for ; Wed, 5 Mar 2014 02:15:36 -0800 (PST) Received: by mail-ee0-f41.google.com with SMTP id t10so337718eei.14 for ; Wed, 05 Mar 2014 02:15:34 -0800 (PST) Content-Disposition: inline In-Reply-To: <1393242980.13131.47.camel@intelbox> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org To: Imre Deak Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Mon, Feb 24, 2014 at 01:56:20PM +0200, Imre Deak wrote: > On Thu, 2014-02-20 at 11:33 -0800, Jesse Barnes wrote: > > On Wed, 19 Feb 2014 14:39:58 +0200 > > Imre Deak wrote: > > = > > > On Wed, 2014-02-19 at 14:35 +0200, Ville Syrj=E4l=E4 wrote: > > > > On Tue, Feb 18, 2014 at 12:02:09AM +0200, Imre Deak wrote: > > > > > The connector detect and get_mode handlers need to access the port > > > > > specific HW blocks to read the EDID etc. Get/put the port power d= omains > > > > > around these handlers. > > > > > = > > > > > Signed-off-by: Imre Deak > > > > > --- > > > > > drivers/gpu/drm/i915/intel_crt.c | 42 ++++++++++++++++++++++++++= ++++++-------- > > > > > drivers/gpu/drm/i915/intel_dp.c | 16 ++++++++++++--- > > > > > drivers/gpu/drm/i915/intel_dsi.c | 13 ++++++++++++- > > > > = > > > > And what about HDMI? > > > = > > > Good catch, I missed that one. > > = > > I wonder if we can catch bits like that using our display reg base > > bits. We could have a platform specific power check for each block to > > do some basic sanity checking on whether the appropriate well was > > enabled and squak if not. > > = > > I just know we'll miss this more than once, and I'm not sure if the > > unclaimed reg stuff will save us on all platforms. > = > Yea, good idea. The register->power well mapping could be part of the > platform specific power well struct and we could assert on the SW state > of the well being 'enabled'. We could add a (start, length) register range (or an array of such ranges) to the power well struct and use that in our reg I/O functions for the display range. If we don't do this for any of the registers in the forcewake range the impact should be fairly minimal I hope ... -Daniel -- = Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch