From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [PATCH 18/19] drm/i915: move hsw power domain comment to its right place Date: Wed, 5 Mar 2014 11:34:19 +0100 Message-ID: <20140305103419.GW17001@phenom.ffwll.local> References: <1392674540-10915-1-git-send-email-imre.deak@intel.com> <1392674540-10915-19-git-send-email-imre.deak@intel.com> <20140220115307.77c5e32a@jbarnes-desktop> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail-ea0-f175.google.com (mail-ea0-f175.google.com [209.85.215.175]) by gabe.freedesktop.org (Postfix) with ESMTP id 8519AFA4C0 for ; Wed, 5 Mar 2014 02:34:27 -0800 (PST) Received: by mail-ea0-f175.google.com with SMTP id d10so918054eaj.34 for ; Wed, 05 Mar 2014 02:34:25 -0800 (PST) Content-Disposition: inline In-Reply-To: <20140220115307.77c5e32a@jbarnes-desktop> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org To: Jesse Barnes Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Thu, Feb 20, 2014 at 11:53:07AM -0800, Jesse Barnes wrote: > On Tue, 18 Feb 2014 00:02:19 +0200 > Imre Deak wrote: > > > Signed-off-by: Imre Deak > > --- > > drivers/gpu/drm/i915/intel_pm.c | 12 ++++++------ > > 1 file changed, 6 insertions(+), 6 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > > index 21ccf89..68f58e5 100644 > > --- a/drivers/gpu/drm/i915/intel_pm.c > > +++ b/drivers/gpu/drm/i915/intel_pm.c > > @@ -5213,6 +5213,12 @@ bool intel_display_power_enabled(struct drm_i915_private *dev_priv, > > return is_enabled; > > } > > > > +/* > > + * Starting with Haswell, we have a "Power Down Well" that can be turned off > > + * when not needed anymore. We have 4 registers that can request the power well > > + * to be enabled, and it will only be disabled if none of the registers is > > + * requesting it to be enabled. > > + */ > > static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv) > > { > > struct drm_device *dev = dev_priv->dev; > > @@ -5556,12 +5562,6 @@ static void intel_power_domains_resume(struct drm_i915_private *dev_priv) > > mutex_unlock(&power_domains->lock); > > } > > > > -/* > > - * Starting with Haswell, we have a "Power Down Well" that can be turned off > > - * when not needed anymore. We have 4 registers that can request the power well > > - * to be enabled, and it will only be disabled if none of the registers is > > - * requesting it to be enabled. > > - */ > > void intel_power_domains_init_hw(struct drm_i915_private *dev_priv) > > { > > /* For now, we need the power well to be always enabled. */ > > Reviewed-by: Jesse Barnes Queued for -next, thanks for the patch. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch