From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [PATCH 11/11] drm/i915: assert we're not runtime suspended when writing registers Date: Wed, 5 Mar 2014 14:44:18 +0100 Message-ID: <20140305134418.GO17001@phenom.ffwll.local> References: <1393001548-2883-1-git-send-email-przanoni@gmail.com> <1393001548-2883-12-git-send-email-przanoni@gmail.com> <1393600572.3479.64.camel@intelbox> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail-ea0-f180.google.com (mail-ea0-f180.google.com [209.85.215.180]) by gabe.freedesktop.org (Postfix) with ESMTP id 1DB8EFA6D9 for ; Wed, 5 Mar 2014 05:44:22 -0800 (PST) Received: by mail-ea0-f180.google.com with SMTP id m10so1039927eaj.11 for ; Wed, 05 Mar 2014 05:44:22 -0800 (PST) Content-Disposition: inline In-Reply-To: <1393600572.3479.64.camel@intelbox> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org To: Imre Deak Cc: intel-gfx@lists.freedesktop.org, Paulo Zanoni List-Id: intel-gfx@lists.freedesktop.org On Fri, Feb 28, 2014 at 05:16:12PM +0200, Imre Deak wrote: > On Fri, 2014-02-21 at 13:52 -0300, Paulo Zanoni wrote: > > From: Paulo Zanoni > > > > I could swear this was already happening in the current code... > > > > Also, put the reads and writes in a generic place, so we don't forget > > it again when we add runtime PM support to new platforms. > > > > Signed-off-by: Paulo Zanoni > > In subject: s/writing/reading/ . Otherwise: > Reviewed-by: Imre Deak > > > --- > > drivers/gpu/drm/i915/intel_uncore.c | 4 ++-- > > 1 file changed, 2 insertions(+), 2 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c > > index c3a4d6f..acce5e8 100644 > > --- a/drivers/gpu/drm/i915/intel_uncore.c > > +++ b/drivers/gpu/drm/i915/intel_uncore.c > > @@ -470,6 +470,7 @@ hsw_unclaimed_reg_check(struct drm_i915_private *dev_priv, u32 reg) > > #define REG_READ_HEADER(x) \ > > unsigned long irqflags; \ > > u##x val = 0; \ > > + assert_device_not_suspended(dev_priv); \ > > spin_lock_irqsave(&dev_priv->uncore.lock, irqflags) Hm, shouldn't we do this in the generic part of the register r/w functions? Anyway, I've merged all patches in this series to dinq with the exception of the two I've complained about. Thanks, Daniel > > > > #define REG_READ_FOOTER \ > > @@ -568,6 +569,7 @@ __gen4_read(64) > > #define REG_WRITE_HEADER \ > > unsigned long irqflags; \ > > trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \ > > + assert_device_not_suspended(dev_priv); \ > > spin_lock_irqsave(&dev_priv->uncore.lock, irqflags) > > > > #define REG_WRITE_FOOTER \ > > @@ -598,7 +600,6 @@ gen6_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace > > if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ > > __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \ > > } \ > > - assert_device_not_suspended(dev_priv); \ > > __raw_i915_write##x(dev_priv, reg, val); \ > > if (unlikely(__fifo_ret)) { \ > > gen6_gt_check_fifodbg(dev_priv); \ > > @@ -614,7 +615,6 @@ hsw_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) > > if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ > > __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \ > > } \ > > - assert_device_not_suspended(dev_priv); \ > > hsw_unclaimed_reg_clear(dev_priv, reg); \ > > __raw_i915_write##x(dev_priv, reg, val); \ > > if (unlikely(__fifo_ret)) { \ > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch