From: Ben Widawsky <benjamin.widawsky@intel.com>
To: Daniel Vetter <daniel@ffwll.ch>
Cc: Intel GFX <intel-gfx@lists.freedesktop.org>,
Ben Widawsky <ben@bwidawsk.net>
Subject: Re: [PATCH] drm/i915/bdw: MU_FLUSH_DW a qword instead of dword
Date: Wed, 5 Mar 2014 11:05:15 -0800 [thread overview]
Message-ID: <20140305190515.GA21029@intel.com> (raw)
In-Reply-To: <20140305183311.GX17001@phenom.ffwll.local>
On Wed, Mar 05, 2014 at 07:33:11PM +0100, Daniel Vetter wrote:
> On Wed, Mar 05, 2014 at 09:24:34AM +0000, Chris Wilson wrote:
> > On Tue, Mar 04, 2014 at 09:38:56AM -0800, Ben Widawsky wrote:
> > > The actual post sync op is "Write Immediate Data QWord." It is therefore
> > > arguable that we should have always done a qword write.
> >
> > Not really since the spec explicitly says that we can choose either a
> > dword or qword write. Note that qword writes also currently require a
> > 64 byte alignment.
>
> Yeah, that's also my reading of the spec - the lenght field selects
> whether the hw does a qword or dword write, and the qword needs to be
> specially aligned.
> -Daniel
I think both of you only read this sentence, where I said it was
"arguable." The rest of the commit message was what actually mattered.
--
Ben Widawsky, Intel Open Source Technology Center
next prev parent reply other threads:[~2014-03-05 19:05 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-03-04 17:38 [PATCH] drm/i915/bdw: MU_FLUSH_DW a qword instead of dword Ben Widawsky
2014-03-05 9:24 ` Chris Wilson
2014-03-05 18:33 ` Daniel Vetter
2014-03-05 19:05 ` Ben Widawsky [this message]
2014-03-05 22:30 ` Chris Wilson
2014-03-05 22:38 ` Ben Widawsky
2014-03-05 23:13 ` Damien Lespiau
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