[PATCH] drm/i915/bdw: Add FBC support

[PATCH] drm/i915/bdw: Add FBC support

[Ben Widawsky]

This got lost when we shuffled around our internal branch and
GEN7_FEATURES macro. There were no HW changes to support FBC, so we just
need to set the flag.

Cc: Daisy Sun <daisy.sun@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
 drivers/gpu/drm/i915/i915_drv.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index ebeefdd..f3b9902 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -265,6 +265,7 @@ static const struct intel_device_info intel_broadwell_d_info = {
 	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 	.has_llc = 1,
 	.has_ddi = 1,
+	.has_fbc = 1,
 	GEN_DEFAULT_PIPEOFFSETS,
 };
 
@@ -274,6 +275,7 @@ static const struct intel_device_info intel_broadwell_m_info = {
 	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 	.has_llc = 1,
 	.has_ddi = 1,
+	.has_fbc = 1,
 	GEN_DEFAULT_PIPEOFFSETS,
 };
 
-- 
1.9.0

[PATCH] [v2] drm/i915/bdw: Add FBC support

[Ben Widawsky]

This got lost when we shuffled around our internal branch and
GEN7_FEATURES macro. There were no HW changes to support FBC, so we just
need to set the flag.

v2: Don't allow FBC for any pipe but A on platforms with DDI. (Paulo)

Cc: Daisy Sun <daisy.sun@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
 drivers/gpu/drm/i915/i915_drv.c | 2 ++
 drivers/gpu/drm/i915/intel_pm.c | 2 +-
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index a18c27d..dc44048 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -265,6 +265,7 @@ static const struct intel_device_info intel_broadwell_d_info = {
 	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 	.has_llc = 1,
 	.has_ddi = 1,
+	.has_fbc = 1,
 	GEN_DEFAULT_PIPEOFFSETS,
 };
 
@@ -274,6 +275,7 @@ static const struct intel_device_info intel_broadwell_m_info = {
 	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 	.has_llc = 1,
 	.has_ddi = 1,
+	.has_fbc = 1,
 	GEN_DEFAULT_PIPEOFFSETS,
 };
 
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index a03a12e..4f01b04 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -540,7 +540,7 @@ void intel_update_fbc(struct drm_device *dev)
 			DRM_DEBUG_KMS("mode too large for compression, disabling\n");
 		goto out_disable;
 	}
-	if ((INTEL_INFO(dev)->gen < 4 || IS_HASWELL(dev)) &&
+	if ((INTEL_INFO(dev)->gen < 4 || HAS_DDI(dev)) &&
 	    intel_crtc->plane != PLANE_A) {
 		if (set_no_fbc_reason(dev_priv, FBC_BAD_PLANE))
 			DRM_DEBUG_KMS("plane not A, disabling compression\n");
-- 
1.9.0

Re: [PATCH] [v2] drm/i915/bdw: Add FBC support

[Paulo Zanoni]

2014-02-20 21:01 GMT-03:00 Ben Widawsky <benjamin.widawsky@intel.com>:
> This got lost when we shuffled around our internal branch and
> GEN7_FEATURES macro. There were no HW changes to support FBC, so we just
> need to set the flag.
>
> v2: Don't allow FBC for any pipe but A on platforms with DDI. (Paulo)
>
> Cc: Daisy Sun <daisy.sun@intel.com>
> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>

Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_drv.c | 2 ++
>  drivers/gpu/drm/i915/intel_pm.c | 2 +-
>  2 files changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index a18c27d..dc44048 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -265,6 +265,7 @@ static const struct intel_device_info intel_broadwell_d_info = {
>         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
>         .has_llc = 1,
>         .has_ddi = 1,
> +       .has_fbc = 1,
>         GEN_DEFAULT_PIPEOFFSETS,
>  };
>
> @@ -274,6 +275,7 @@ static const struct intel_device_info intel_broadwell_m_info = {
>         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
>         .has_llc = 1,
>         .has_ddi = 1,
> +       .has_fbc = 1,
>         GEN_DEFAULT_PIPEOFFSETS,
>  };
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index a03a12e..4f01b04 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -540,7 +540,7 @@ void intel_update_fbc(struct drm_device *dev)
>                         DRM_DEBUG_KMS("mode too large for compression, disabling\n");
>                 goto out_disable;
>         }
> -       if ((INTEL_INFO(dev)->gen < 4 || IS_HASWELL(dev)) &&
> +       if ((INTEL_INFO(dev)->gen < 4 || HAS_DDI(dev)) &&
>             intel_crtc->plane != PLANE_A) {
>                 if (set_no_fbc_reason(dev_priv, FBC_BAD_PLANE))
>                         DRM_DEBUG_KMS("plane not A, disabling compression\n");
> --
> 1.9.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
Paulo Zanoni

Re: [PATCH] [v2] drm/i915/bdw: Add FBC support

[Daniel Vetter]

On Fri, Feb 21, 2014 at 04:06:47PM -0300, Paulo Zanoni wrote:
> 2014-02-20 21:01 GMT-03:00 Ben Widawsky <benjamin.widawsky@intel.com>:
> > This got lost when we shuffled around our internal branch and
> > GEN7_FEATURES macro. There were no HW changes to support FBC, so we just
> > need to set the flag.
> >
> > v2: Don't allow FBC for any pipe but A on platforms with DDI. (Paulo)
> >
> > Cc: Daisy Sun <daisy.sun@intel.com>
> > Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
> 
> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>

Have you guys run the fbc igt testcase to make sure it actually works? In
case it's broken I'll back it out again ...

Queued for -next, thanks for the patch.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH] [v2] drm/i915/bdw: Add FBC support

[Ben Widawsky]

On Wed, Mar 05, 2014 at 12:00:18PM +0100, Daniel Vetter wrote:
> On Fri, Feb 21, 2014 at 04:06:47PM -0300, Paulo Zanoni wrote:
> > 2014-02-20 21:01 GMT-03:00 Ben Widawsky <benjamin.widawsky@intel.com>:
> > > This got lost when we shuffled around our internal branch and
> > > GEN7_FEATURES macro. There were no HW changes to support FBC, so we just
> > > need to set the flag.
> > >
> > > v2: Don't allow FBC for any pipe but A on platforms with DDI. (Paulo)
> > >
> > > Cc: Daisy Sun <daisy.sun@intel.com>
> > > Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
> > 
> > Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> 
> Have you guys run the fbc igt testcase to make sure it actually works? In
> case it's broken I'll back it out again ...
> 
> Queued for -next, thanks for the patch.
> -Daniel

Daisy, I was led to believe you actually tested this. Is that correct?

Daniel, BTW, we have an unimplemented FBC bugfix (basically disable) on
HSW that carries over to BDW. It was not implemented last time I checked
anyway. I tried to implement it, but I don't know the code well enough.
Feel free to sign me up for review if someone else does it.

Also, 4k displays have some issue with FBC. So we'll need to address
that.

-- 
Ben Widawsky, Intel Open Source Technology Center