From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [PATCH 6/8] drm/i915: don't bother enabling swizzle bits on gen7+ Date: Sat, 8 Mar 2014 11:36:24 +0100 Message-ID: <20140308103624.GN25837@phenom.ffwll.local> References: <1394211475-2646-1-git-send-email-jbarnes@virtuousgeek.org> <1394211475-2646-6-git-send-email-jbarnes@virtuousgeek.org> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mail-ee0-f44.google.com (mail-ee0-f44.google.com [74.125.83.44]) by gabe.freedesktop.org (Postfix) with ESMTP id CFD18FAD6C for ; Sat, 8 Mar 2014 02:36:28 -0800 (PST) Received: by mail-ee0-f44.google.com with SMTP id e49so2174509eek.31 for ; Sat, 08 Mar 2014 02:36:28 -0800 (PST) Content-Disposition: inline In-Reply-To: <1394211475-2646-6-git-send-email-jbarnes@virtuousgeek.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org To: Jesse Barnes Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Fri, Mar 07, 2014 at 08:57:53AM -0800, Jesse Barnes wrote: > As of IVB, the memory controller does internal swizzling already, so we > shouldn't need to enable these. Based on an earlier fix from Kristian. > = > Reported-by: Kristian H=F8gsberg > Signed-off-by: Jesse Barnes Imo the right approach here is to check whether any of the preserved/inherited framebuffers has tiling enabled, and if so we need to preserve the swizzling mode the bios has set. Also this should be done on gen6+ since those are the machines where swizzling can be changed. -Daniel > --- > drivers/gpu/drm/i915/i915_gem.c | 7 +++---- > drivers/gpu/drm/i915/i915_gem_tiling.c | 2 +- > 2 files changed, 4 insertions(+), 5 deletions(-) > = > diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_= gem.c > index 18ea6bc..dcf4b01 100644 > --- a/drivers/gpu/drm/i915/i915_gem.c > +++ b/drivers/gpu/drm/i915/i915_gem.c > @@ -4296,6 +4296,9 @@ void i915_gem_init_swizzling(struct drm_device *dev) > dev_priv->mm.bit_6_swizzle_x =3D=3D I915_BIT_6_SWIZZLE_NONE) > return; > = > + if (INTEL_INFO(dev)->gen >=3D 7) > + return; > + > I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | > DISP_TILE_SURFACE_SWIZZLING); > = > @@ -4305,10 +4308,6 @@ void i915_gem_init_swizzling(struct drm_device *de= v) > I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL); > if (IS_GEN6(dev)) > I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB)); > - else if (IS_GEN7(dev)) > - I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB)); > - else if (IS_GEN8(dev)) > - I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW)); > else > BUG(); > } > diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i91= 5/i915_gem_tiling.c > index eb99358..05c5d98 100644 > --- a/drivers/gpu/drm/i915/i915_gem_tiling.c > +++ b/drivers/gpu/drm/i915/i915_gem_tiling.c > @@ -91,7 +91,7 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev) > uint32_t swizzle_x =3D I915_BIT_6_SWIZZLE_UNKNOWN; > uint32_t swizzle_y =3D I915_BIT_6_SWIZZLE_UNKNOWN; > = > - if (IS_VALLEYVIEW(dev)) { > + if (INTEL_INFO(dev)->gen >=3D 7) { > swizzle_x =3D I915_BIT_6_SWIZZLE_NONE; > swizzle_y =3D I915_BIT_6_SWIZZLE_NONE; > } else if (INTEL_INFO(dev)->gen >=3D 6) { > -- = > 1.8.4.2 > = > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- = Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch