From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ben Widawsky Subject: Re: [PATCH] drm/i915: Fail gpu reset if the forcewake fifo hasn't drained Date: Sat, 8 Mar 2014 12:02:39 -0800 Message-ID: <20140308200239.GB16546@bwidawsk.net> References: <1394222943-7241-1-git-send-email-daniel.vetter@ffwll.ch> <20140307213556.GG25837@phenom.ffwll.local> <20140308185041.GA16066@bwidawsk.net> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail.bwidawsk.net (bwidawsk.net [166.78.191.112]) by gabe.freedesktop.org (Postfix) with ESMTP id A90F8FA98A for ; Sat, 8 Mar 2014 12:02:53 -0800 (PST) Content-Disposition: inline In-Reply-To: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org To: Daniel Vetter Cc: Intel Graphics Development , Mika Kuoppala List-Id: intel-gfx@lists.freedesktop.org On Sat, Mar 08, 2014 at 08:58:24PM +0100, Daniel Vetter wrote: > On Sat, Mar 8, 2014 at 7:50 PM, Ben Widawsky wrote: > > I've seen this too. Though I think the WARN does coincide with what the > > docs state - it doesn't seem to match reality. So I totally agree this > > is the right course. > > > > However, for my curiosity, Chris, can you elaborate on why you think it > > doesn't make sense? > > Our current fifo code would be broken - we stall for the fifo entries > to refill if the value drops below NUM_FIFO_ENTRIES_RESERVED. Hence if > the register value is zero right after reset, something is terribly > broken. > -Daniel Oh that's right. fifo_entries should be MAX, not 0. Wonder if that one would WARN. Anyway, I'm not actually sure if MAX is always known, so probably a stupid idea anyway. -- Ben Widawsky, Intel Open Source Technology Center