From mboxrd@z Thu Jan 1 00:00:00 1970 From: Bjorn Helgaas Subject: Re: agp/intel: can't ioremap flush page - no chipset flushing Date: Mon, 10 Mar 2014 12:24:31 -0600 Message-ID: <20140310182431.GA11424@google.com> References: <1391951759.6036.7.camel@artifact> <1391952344.25424.4.camel@x220> <1394185698.5608.5.camel@x41> <1394212609.1987.6.camel@x41> <20140307204021.GA9822@google.com> <1394289877.31006.2.camel@x41> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail-ie0-f176.google.com (mail-ie0-f176.google.com [209.85.223.176]) by gabe.freedesktop.org (Postfix) with ESMTP id B96FFFA6E9 for ; Mon, 10 Mar 2014 11:24:37 -0700 (PDT) Received: by mail-ie0-f176.google.com with SMTP id rd18so7680701iec.21 for ; Mon, 10 Mar 2014 11:24:36 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1394289877.31006.2.camel@x41> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org To: Paul Bolle Cc: David Airlie , Daniel Vetter , intel-gfx , Linux Kernel Mailing List , linux-pci@vger.kernel.org, Yinghai Lu List-Id: intel-gfx@lists.freedesktop.org [+cc linux-pci] On Sat, Mar 08, 2014 at 03:44:37PM +0100, Paul Bolle wrote: > Bjorn Helgaas schreef op za 08-03-2014 om 07:12 [-0700]: > > I assume you have CONFIG_PHYS_ADDR_T_64BIT=n (which is perfectly > > legal); let me know if otherwise. > > $ grep CONFIG_PHYS_ADDR_T_64BIT /boot/config-3.14.0-0.rc5.1.local2.fc20.i686 > # CONFIG_PHYS_ADDR_T_64BIT is not set > > So, yes, CONFIG_PHYS_ADDR_T_64BIT=n here. Thanks. Can you try the patch below? I think it should fix the problem. PCI: Don't check resource_size() in pci_bus_alloc_resource() From: Bjorn Helgaas When resource_size_t is 32 bits wide, e.g., when CONFIG_PHYS_ADDR_T_64BIT is not defined, resource_size() on [mem 0x00000000-0xffffffff] returns 0 because (r->end - r->start + 1) overflows. Therefore, we can't use "resource_size() == 0" to decide that allocation from this resource will fail. allocate_resource() should fail anyway if it can't satisfy the address constraints, so we should just depend on that. A [mem 0x00000000-0xffffffff] bus resource is obviously not really valid, but we do fall back to it as a default when we don't have information about host bridge apertures. Link: https://bugzilla.kernel.org/show_bug.cgi?id=71611 Fixes: f75b99d5a77d PCI: Enforce bus address limits in resource allocation Signed-off-by: Bjorn Helgaas --- drivers/pci/bus.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/pci/bus.c b/drivers/pci/bus.c index 00660cc502c5..38901665c770 100644 --- a/drivers/pci/bus.c +++ b/drivers/pci/bus.c @@ -162,8 +162,6 @@ static int pci_bus_alloc_from_region(struct pci_bus *bus, struct resource *res, avail = *r; pci_clip_resource_to_region(bus, &avail, region); - if (!resource_size(&avail)) - continue; /* * "min" is typically PCIBIOS_MIN_IO or PCIBIOS_MIN_MEM to