From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH 1/3] drm/i915: Track the enabled PM interrupts in dev_priv. Date: Thu, 13 Mar 2014 20:59:48 +0200 Message-ID: <20140313185948.GS20292@intel.com> References: <531718EF.3060201@intel.com> <1394726418-10831-1-git-send-email-deepak.s@linux.intel.com> <1394726418-10831-2-git-send-email-deepak.s@linux.intel.com> <20140313181648.GP20292@intel.com> <5321FC52.1000707@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTP id BC2DEFB3AC for ; Thu, 13 Mar 2014 12:00:08 -0700 (PDT) Content-Disposition: inline In-Reply-To: <5321FC52.1000707@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org To: "S, Deepak" Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Fri, Mar 14, 2014 at 12:13:30AM +0530, S, Deepak wrote: > = > = > On 3/13/2014 11:46 PM, Ville Syrj=E4l=E4 wrote: > > On Thu, Mar 13, 2014 at 09:30:16PM +0530, deepak.s@linux.intel.com wrot= e: > >> From: Deepak S > >> > >> When we use different rps events for different platform or due to wa, = we > >> mgiht end up doing (vs) everywahere. Insted of this, Let's use a varia= ble > >> in dev_priv to track the enabled PM interrupts > >> > >> Signed-off-by: Deepak S > >> --- > >> drivers/gpu/drm/i915/i915_drv.h | 1 + > >> drivers/gpu/drm/i915/i915_irq.c | 14 +++++++------- > >> drivers/gpu/drm/i915/intel_pm.c | 14 +++++++++----- > >> 3 files changed, 17 insertions(+), 12 deletions(-) > >> > >> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i9= 15_drv.h > >> index 70fbe90..d522313 100644 > > > >> @@ -3311,6 +3311,8 @@ static void gen8_enable_rps(struct drm_device *d= ev) > >> GEN6_RP_UP_BUSY_AVG | > >> GEN6_RP_DOWN_IDLE_AVG); > >> > >> + dev_priv->pm_rps_events =3D GEN6_PM_RPS_EVENTS; > >> + > >> /* 6: Ring frequency + overclocking (our driver does this later */ > >> > >> gen6_set_rps(dev, (I915_READ(GEN6_GT_PERF_STATUS) & 0xff00) >> 8); > >> @@ -3430,6 +3432,7 @@ static void gen6_enable_rps(struct drm_device *d= ev) > >> dev_priv->rps.power =3D HIGH_POWER; /* force a reset */ > >> gen6_set_rps(dev_priv->dev, dev_priv->rps.min_delay); > >> > >> + dev_priv->pm_rps_events =3D GEN6_PM_RPS_EVENTS; > >> gen6_enable_rps_interrupts(dev); > >> > >> rc6vids =3D 0; > >> @@ -3688,6 +3691,7 @@ static void valleyview_enable_rps(struct drm_dev= ice *dev) > >> dev_priv->rps.rp_up_masked =3D false; > >> dev_priv->rps.rp_down_masked =3D false; > >> > >> + dev_priv->pm_rps_events =3D GEN6_PM_RPS_EVENTS; > >> gen6_enable_rps_interrupts(dev); > >> > >> gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL); > > > > I think we need to initialize pm_rps_events somewhere earlier since we > > depend on it already in irq postinstall. Othwewise the patch looks > > good. > Adding it in functions "intel_uncore_early_sanitize" or "pm_init" as = > this gets executed before irq_install in driver_load? intel_irq_init() might be a good choice since that's where we also initialize the rps.work, and then it's clear it gets executed before any other irq setup code. -- = Ville Syrj=E4l=E4 Intel OTC