From mboxrd@z Thu Jan 1 00:00:00 1970 From: Damien Lespiau Subject: Re: [PATCH v2 1/3] drm/i915/vlv: Added a rendering specific Hw WA 'WaTlbInvalidateStoreDataBefore' Date: Fri, 21 Mar 2014 11:59:26 +0000 Message-ID: <20140321115926.GC7294@strange.amr.corp.intel.com> References: <1391775732-7431-1-git-send-email-akash.goel@intel.com> <1391775732-7431-2-git-send-email-akash.goel@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTP id B0B0D6E2D3 for ; Fri, 21 Mar 2014 04:59:53 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1391775732-7431-2-git-send-email-akash.goel@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: akash.goel@intel.com Cc: intel-gfx@lists.freedesktop.org, sourab.gupta@intel.com List-Id: intel-gfx@lists.freedesktop.org On Fri, Feb 07, 2014 at 05:52:10PM +0530, akash.goel@intel.com wrote: > From: Akash Goel > > Added a new rendering specific Workaround 'WaTlbInvalidateStoreDataBefore'. > In this WA, before pipecontrol with TLB invalidate set, need to add 2 MI > Store data commands. > > v2: Modified the WA comment. (Ville) > > Signed-off-by: Akash Goel > --- > drivers/gpu/drm/i915/intel_ringbuffer.c | 23 +++++++++++++++++++++++ > 1 file changed, 23 insertions(+) > > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c > index d897a19..2ac6600 100644 > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c > @@ -2183,6 +2183,29 @@ intel_ring_invalidate_all_caches(struct intel_ring_buffer *ring) > uint32_t flush_domains; > int ret; > > + if (IS_VALLEYVIEW(ring->dev)) { > + /* > + * WaTlbInvalidateStoreDataBefore > + * Before pipecontrol with TLB invalidate set, need 2 store > + * data commands (such as MI_STORE_DATA_IMM or MI_STORE_DATA_INDEX) > + * Without this, hardware cannot guarantee the command after the > + * PIPE_CONTROL with TLB inv will not use the old TLB values. > + * FIXME, should also apply to snb, ivb > + */ We have a small syntax to indicate for which platform a W/A has been implemented so a script in intel-gpu-tool can pick them up and make a list. It's a bit low-fi, but has proven to be handy to quickly check what we implement for a specific platform. So this should be WaTlbInvalidateStoreDataBefore:vlv This script works like this: $ /path/to/intel-gpu-tools/scripts/list-workarounds -p vlv /path/to/kernel WaCatErrorRejectionIssue WaDisableAsyncFlipPerfMode WaDisableBackToBackFlipFix WaDisableDopClockGating WaDisableEarlyCull WaDisableL3Bank2xClockGate WaDisablePSDDualDispatchEnable ... -- Damien