From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH v2 1/3] drm/i915: Track the enabled PM interrupts in dev_priv. Date: Mon, 24 Mar 2014 21:26:52 +0200 Message-ID: <20140324192652.GK21652@intel.com> References: <20140313185948.GS20292@intel.com> <1394895204-13581-1-git-send-email-deepak.s@linux.intel.com> <1394895204-13581-2-git-send-email-deepak.s@linux.intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTP id 2E95389C59 for ; Mon, 24 Mar 2014 12:27:01 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1394895204-13581-2-git-send-email-deepak.s@linux.intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: deepak.s@linux.intel.com Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Sat, Mar 15, 2014 at 08:23:22PM +0530, deepak.s@linux.intel.com wrote: > From: Deepak S > = > When we use different rps events for different platform or due to wa, we > mgiht end up doing (vs) everywahere. Insted of this, Let's use a variable > in dev_priv to track the enabled PM interrupts > = > v2: Initialize pm_rps_events in intel_irq_init() (Ville). > = > Signed-off-by: Deepak S Reviewed-by: Ville Syrj=E4l=E4 > --- > drivers/gpu/drm/i915/i915_drv.h | 1 + > drivers/gpu/drm/i915/i915_irq.c | 17 ++++++++++------- > drivers/gpu/drm/i915/intel_pm.c | 11 ++++++----- > 3 files changed, 17 insertions(+), 12 deletions(-) > = > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_= drv.h > index 70fbe90..d522313 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -1487,6 +1487,7 @@ typedef struct drm_i915_private { > }; > u32 gt_irq_mask; > u32 pm_irq_mask; > + u32 pm_rps_events; > u32 pipestat_irq_mask[I915_MAX_PIPES]; > = > struct work_struct hotplug_work; > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_= irq.c > index 37f852d..00b3bfc 100644 > --- a/drivers/gpu/drm/i915/i915_irq.c > +++ b/drivers/gpu/drm/i915/i915_irq.c > @@ -1132,13 +1132,13 @@ static void gen6_pm_rps_work(struct work_struct *= work) > pm_iir =3D dev_priv->rps.pm_iir; > dev_priv->rps.pm_iir =3D 0; > /* Make sure not to corrupt PMIMR state used by ringbuffer code */ > - snb_enable_pm_irq(dev_priv, GEN6_PM_RPS_EVENTS); > + snb_enable_pm_irq(dev_priv, dev_priv->pm_rps_events); > spin_unlock_irq(&dev_priv->irq_lock); > = > /* Make sure we didn't queue anything we're not going to process. */ > - WARN_ON(pm_iir & ~GEN6_PM_RPS_EVENTS); > + WARN_ON(pm_iir & ~dev_priv->pm_rps_events); > = > - if ((pm_iir & GEN6_PM_RPS_EVENTS) =3D=3D 0) > + if ((pm_iir & dev_priv->pm_rps_events) =3D=3D 0) > return; > = > mutex_lock(&dev_priv->rps.hw_lock); > @@ -1555,10 +1555,10 @@ static void i9xx_pipe_crc_irq_handler(struct drm_= device *dev, enum pipe pipe) > * the work queue. */ > static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 = pm_iir) > { > - if (pm_iir & GEN6_PM_RPS_EVENTS) { > + if (pm_iir & dev_priv->pm_rps_events) { > spin_lock(&dev_priv->irq_lock); > - dev_priv->rps.pm_iir |=3D pm_iir & GEN6_PM_RPS_EVENTS; > - snb_disable_pm_irq(dev_priv, pm_iir & GEN6_PM_RPS_EVENTS); > + dev_priv->rps.pm_iir |=3D pm_iir & dev_priv->pm_rps_events; > + snb_disable_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events); > spin_unlock(&dev_priv->irq_lock); > = > queue_work(dev_priv->wq, &dev_priv->rps.work); > @@ -2983,7 +2983,7 @@ static void gen5_gt_irq_postinstall(struct drm_devi= ce *dev) > POSTING_READ(GTIER); > = > if (INTEL_INFO(dev)->gen >=3D 6) { > - pm_irqs |=3D GEN6_PM_RPS_EVENTS; > + pm_irqs |=3D dev_priv->pm_rps_events; > = > if (HAS_VEBOX(dev)) > pm_irqs |=3D PM_VEBOX_USER_INTERRUPT; > @@ -4030,6 +4030,9 @@ void intel_irq_init(struct drm_device *dev) > INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work); > INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work); > = > + /* Let's track the enabled rps events */ > + dev_priv->pm_rps_events =3D GEN6_PM_RPS_EVENTS; > + > setup_timer(&dev_priv->gpu_error.hangcheck_timer, > i915_hangcheck_elapsed, > (unsigned long) dev); > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel= _pm.c > index ad58ce3..95b133a 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -3160,7 +3160,8 @@ static void gen6_disable_rps_interrupts(struct drm_= device *dev) > struct drm_i915_private *dev_priv =3D dev->dev_private; > = > I915_WRITE(GEN6_PMINTRMSK, 0xffffffff); > - I915_WRITE(GEN6_PMIER, I915_READ(GEN6_PMIER) & ~GEN6_PM_RPS_EVENTS); > + I915_WRITE(GEN6_PMIER, I915_READ(GEN6_PMIER) & > + ~dev_priv->pm_rps_events); > /* Complete PM interrupt masking here doesn't race with the rps work > * item again unmasking PM interrupts because that is using a different > * register (PMIMR) to mask PM interrupts. The only risk is in leaving > @@ -3170,7 +3171,7 @@ static void gen6_disable_rps_interrupts(struct drm_= device *dev) > dev_priv->rps.pm_iir =3D 0; > spin_unlock_irq(&dev_priv->irq_lock); > = > - I915_WRITE(GEN6_PMIIR, GEN6_PM_RPS_EVENTS); > + I915_WRITE(GEN6_PMIIR, dev_priv->pm_rps_events); > } > = > static void gen6_disable_rps(struct drm_device *dev) > @@ -3232,12 +3233,12 @@ static void gen6_enable_rps_interrupts(struct drm= _device *dev) > = > spin_lock_irq(&dev_priv->irq_lock); > WARN_ON(dev_priv->rps.pm_iir); > - snb_enable_pm_irq(dev_priv, GEN6_PM_RPS_EVENTS); > - I915_WRITE(GEN6_PMIIR, GEN6_PM_RPS_EVENTS); > + snb_enable_pm_irq(dev_priv, dev_priv->pm_rps_events); > + I915_WRITE(GEN6_PMIIR, dev_priv->pm_rps_events); > spin_unlock_irq(&dev_priv->irq_lock); > = > /* only unmask PM interrupts we need. Mask all others. */ > - enabled_intrs =3D GEN6_PM_RPS_EVENTS; > + enabled_intrs =3D dev_priv->pm_rps_events; > = > /* IVB and SNB hard hangs on looping batchbuffer > * if GEN6_PM_UP_EI_EXPIRED is masked. > -- = > 1.8.4.2 > = > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- = Ville Syrj=E4l=E4 Intel OTC