From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH v2 4/6] drm/i915/vlv: Remove the enabling of VS_TIMER_DISPATCH bit in MI MODE reg Date: Tue, 25 Mar 2014 13:33:51 +0200 Message-ID: <20140325113351.GM21652@intel.com> References: <20140324180116.GS4366@nuc-i3427.alporthouse.com> <1395685702-8070-1-git-send-email-sourab.gupta@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTP id 06CA96E199 for ; Tue, 25 Mar 2014 04:33:55 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1395685702-8070-1-git-send-email-sourab.gupta@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: sourab.gupta@intel.com Cc: Akash Goel , Daniel Vetter , intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Mon, Mar 24, 2014 at 11:58:22PM +0530, sourab.gupta@intel.com wrote: > From: Akash Goel > = > Removing the VS_TIMER_DISPATCH bit enable for MI MODE reg for > Gen7 platform as it is not required. > = > v2: Enhancing the scope of the patch to full Gen7 (Chris) > = > Signed-off-by: Akash Goel > Signed-off-by: Sourab Gupta > Tested-by: Chris Wilson # ivb, hsw -Chris > --- > drivers/gpu/drm/i915/intel_ringbuffer.c | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) > = > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i9= 15/intel_ringbuffer.c > index eb4811a..9983802 100644 > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c > @@ -599,7 +599,9 @@ static int init_render_ring(struct intel_ring_buffer = *ring) > int ret =3D init_ring_common(ring); > = > if (INTEL_INFO(dev)->gen > 3) > - I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH)); > + if (!IS_GEN7(dev)) We shouldn't enable this on gen8 either, and while doing that you could avoid the extra indentation by rewriting it as something like this: if (INTEL_INFO(dev)->gen >=3D 4 && INTEL_INFO(dev)->gen < 7) Also you could add the appropriate w/a note while you're touching the code: WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb > + I915_WRITE(MI_MODE, > + _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH)); > = > /* We need to disable the AsyncFlip performance optimisations in order > * to use MI_WAIT_FOR_EVENT within the CS. It should already be > -- = > 1.8.5.1 -- = Ville Syrj=E4l=E4 Intel OTC